TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 163

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.3.2
8.3.3.3
8.3.3.4
Dual Address Transfer
and to external memory is each performed continuously. Each access is the same as normal access
except when the DMAACK[n] signal is asserted.
Single Address Transfer (Fly-by DMA)
device and data writing to external memory or data reading from external memory and data
writing to an external I/O device is performed simultaneously. The following conditions must be
met in order to perform Single Address transfer.
•
•
specifies the transfer direction.
•
•
when performing Burst transfer. Single Address transfer using Burst transfer with SDRAM is not
recommended.
DMADONE* Signal
signalling output signal, or may operate as both of these signals depending on the setting of the
DONE Control Field (DNCTRL) of the DMA Channel Control Register (DMCCRn).
channel when the DMAACK[n] signal for that channel is asserted.
it will operate as follows depending on the setting of the Chain End bit (CHDN) of the DMA
Channel Control Register (DMCCRn).
DMAACK[n] signal for the last DMA transfer in the Link List Command Chain is asserted.
If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices
Please refer to “8.3.8 Dual Address Transfer” for information regarding setting the register.
If the Single Address bit (DMCCRn.SNGAD) is set, either data reading from an external I/O
The Transfer Direction bit (MEMIO) of the DMA Channel Control Register (DMCCRn)
Special attention must be paid to the timing design when the bus clock frequency is high or
The DMADONE* signal operates as either the DMA stop request input signal or the DMA done
The DMADONE* signal is shared by four channels. The DMADONE* channel is valid for a
If the DMADONE* channel is set to be used as an output signal (DMCCRn.DNCTRL = 10/11),
When the Chain End bit (CHDN) is set, the DMADONE* signal is only asserted when the
The data bus widths of the external I/O device and external memory match
Data can be input/output to/from the external I/O device and external memory during the
same clock cycle
From memory to an external I/O device (DMCCRn.MEMIO = “1”)
Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal.
Single Address transfer from memory to an external I/O device (DMCCRn.MEMIO = “0”)
Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal. At
this time, the external I/O device drives the DATA signal instead of the TX4937.
External memory Read operation to an address specified by the DMA Source Address
External memory Write operation to an address specified by the DMA Source Address
8-7
Chapter 8 DMA Controller