TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 183

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:32
Bit
29
28
27
8.4.2
STLTIME/INTRQD
63
47
31
15
Reserved
Mnemonic
USEXFSZ
IMMCHN
LE
R/W
000
30
DMA Channel Control Register (DM0CCRn, DM1CCRn)
Offset address: DMAC0 0xB030 (ch. 0) / 0xB070 (ch. 1) / 0xB0B0 (ch. 2) / 0xB0F0 (ch. 3)
IMMCHN
R/W
29
13
0
Reserved
Immediate Chain
Transfer Set Size
Mode
Little Endian
Field Name
INTENE INTENC INTENT CHNEN XFACT
USEXFSZ
R/W
R/W
28
12
0
0
Figure 8.4.2 DMA Channel Control Register (1/4)
DMAC1 0xB830 (ch. 0) / 0xB870 (ch.1 ) / 0xB8B0 (ch. 2) / 0xB8F0 (ch. 3)
R/W
R/W
LE
27
⎯
11
0
Immediate Chain (Default: 0)
Always set this bit to “1”.
Use Transfer Set Size (Default: 0)
Selects the DMA channel operation mode during Burst DMA transfer.
Refer to “8.3.7.2 Burst Transfer During Single Address Transfer” and
“8.3.8.2 Burst Transfer During Dual Address Transfer” for more
information.
1: The DMA Controller always transfers the amount of data set in
0: The DMA Controller calculates the transfer size so the address set in
Note: In Dual Address Transfer mode, programming this bit to 1 is valid
Little Endian (Default: value that is the opposite of the G-Bus Endian
(CCFG.ENDIAN)
This bit sets the Endian of the channel. Please use the default value as is.
1: Channel operates in the Little Endian mode
0: Channel operates in the Big Endian mode
DBINH SBINH CHRST
R/W
R/W
26
10
DMCCRn.XFSZ for each bus operation. Since alignment to the
boundary of the DMCCRn.XFSZ in the address is not forced when in
this mode, transfers that exceed 32-double-word boundaries are divided
into two operations.
DMSARn and DMDARn (only during Dual Address transfer) can be
aligned to the boundary of the size set in DMCCRn.XFSZ, then
transfers data according to that size.
0
0
only when both the contents of the DMSARn and the DMDARn are
on doubleword boundaries and the contents of the DMCNTRn is a
multiple of eight bytes.
R/W
25
R
0
9
0
R/W
R/W
24
Reserved
Reserved
1
8
0
8-27
RVBYTE ACKPOL
R/W
23
Reserved
0
7
Description
R/W
22
0
6
SMPCHN
REQPL EGREQ CHDN
Chapter 8 DMA Controller
R/W
R/W
21
0
5
0
R/W
20
0
4
XFSZ
R/W
R/W
000
19
0
18
2
DNCTL
R/W
00
MEMIO SNGAD
R/W
17
1
0
Read/Write
R/W
R/W
R/W
EXTRQ
R/W
R/W
48
32
16
0
0
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value