TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 356

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.5 PCI Configuration Space Register
Address
PCI host device only when in the Satellite mode. Table 10.5.1 lists registers contained within the PCI
Configuration Space Register. The registers in the table with a shaded background are those whose values
can be rewritten using EEPROM. (See 10.3.14.)
access from the TX49/H3 core when in the Host mode. Please refer to the explanation of the corresponding
PCI Controller Control registers for more information about these registers. This section only describes the
registers that are accessed from the PCI Configuration Space.
Mode PCI Status Register.
44h-DBh
E4h-FFh
DCh
0Ch
1Ch
2Ch
3Ch
E0h
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
The PCI Configuration Space Register is accessed using PCI Configuration cycles by way of an external
Registers at addresses 0x00 through 0x41 can use the corresponding PCI Controller Control Register to
Also, it is possible to read some of the fields in the Status Register and PMCSR register from the Satellite
Please refer to the PCI Bus Specifications for more information on the PCI Configuration Register.
31
Power Management Capabilities (PMC)
Reserved
Max_Lat
BIST
Table 10.5.1 PCI Configuration Space Register
Subsystem ID
Device ID
Reserved
Status
Memory Space 0 Lower Base Address
Memory Space 0 Upper Base Address
Memory Space 1 Lower Base Address
Memory Space 1 Upper Base Address
Header Type
Class Code
Memory Space 2 Base Address
Reserved
Reserved
Min_Gnt
I/O Space Base Address
10-98
Reserved
Reserved
Reserved
Reserved
Reserved
16
15
(Next_Item_Ptr)
Latency Timer
Retry Timeout
Next Item Ptr
Power Management Control/Status
Interrupt Pin
Value
Subsystem Vendor ID
Register (PMCSR)
Chapter 10 PCI Controller
Vendor ID
Command
Pointer (Cap_Ptr)
Cache Line Size
TRDY Timeout
Interrupt Line
Capability ID
Revision ID
Capabilities
(Cap_ID)
Value
0
Corresponding
P2GM0PLBASE
P2GM0PUBASE
P2GM1PLBASE
P2GM1PUBASE
P2GM2PBASE
P2GIOPBASE
PCICAPPTR
PCISTATUS
G2PTOCNT
PCICCREV
Register
PCICFG1
PCICFG2
PCISID
PCIID
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