TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 274

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.10.2 Chain DMA
Offset Address
3.
4.
5.
6.
that are placed in memory.
Chain Address Field makes it possible to configure a chain list for the DMA command Descriptor.
Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list.
the next DMA Command Descriptor that the Chain Address field automatically points to, then
continues the DMA transfer. Such continuous DMA transfer that uses multiple descriptors in a
chain format is referred to as the Chain DMA mode.
QWORD boundary in memory, this transfer method is more efficient since data can be read by a
single G-Bus Burst Read transaction.
0x00
0x08
0x10
0x18
DMA Command Descriptors are 4 QWORD (32-Byte) data structures indicated in Table 10.3.6
Storing the starting memory address of another DMA Command Descriptor in the Offset 0
When the DMA transfer specified by one DMA Command Descriptor ends, the PDMAC reads
When a DMA Command Descriptor is placed to an address that does not extend across a 32
PDMAC Status Register (PDMSTATUS) Clearing
Clears any remaining status from a previous DMA transfer.
PDMAC Configuration register (PDMCFG) Setting
Clears the Channel Reset bit (CHRST), and makes settings such as the data transfer direction
(XFRDIRC), and the data transfer unit size (XFRSIZE).
DMA Transfer Initiation
Setting the Transfer Active bit (XFRACT) of the PDMAC Configuration Register initiates
DMA transfer.
Termination Report
When the DMA data transfer terminates normally, the Normal Data Transfer Complete bit
(NTCMP) of the PDMAC Status Register (PDMSTATUS) is set. An interrupt is then reported
if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the PDMAC
Configuration Register is set.
If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of
the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the
Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Configuration register is set.
Table 10.3.6 DMA Command Descriptors
Chain Address
G-Bus Address
PCI Bus Address
Count
Field Name
10-16
PDMAC Chain Address Register (PDMCA)
PDMAC G-Bus Address Register (PDMGA)
PDMAC PCI Bus Address Register (PDMPA)
PDMAC Count Register (PDMCTR)
Transfer Destination Register
Chapter 10 PCI Controller