TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 81

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

5.
5.1
5.1.1
Configuration Registers
Detailed Description
Section 5.2 for details of each configuration register. Also refer to sections mentioned in the description
about each bit field.
The configuration registers set up and control the basic functionality of the entire TX4937. Refer to
Detecting G-Bus Timeout
a bus response from the accessed address. If an attempt is made to access an undefined physical address
or if a hardware failure occurs, no bus response is made. If a bus response does not occur, the bus access
will not be completed, leading to a system halt. To solve this problem, the TX4937 is provided with a
G-Bus timeout detection function. This function forcibly stops bus access if no bus response occurs
within the specified time.
enables the G-Bus timeout detection function. If a bus response does not occur within the G-Bus clock
(GBUSCLK) cycle specified in the G-Bus Timeout Time field (CCFG.GTOT), the G-Bus timeout
detection function makes an error response to force the bus access to end. The accessed address is
stored to the timeout error access address register (TOEA).
G-Bus, the Write-Access Bus Error bit (CCFG.BEOW) is set. Enabling interrupt No. 1 in the interrupt
controller makes it possible to post an interrupt to the TX49/H3 core. If a timeout error is detected while
the TX49/H3 core is gaining read access to the bus, a bus error exception occurs in the TX49/H3 core.
accessing the G-Bus, an error bit in that controller is set, which can be used to post an interrupt. Refer to
the descriptions of each controller for details.
timeout detection feature is disabled.
The G-bus is an internal bus of the TX4937. Access to each address on the G-Bus is completed upon
Setting the G-Bus Timeout Error Detection bit (CCFG.TOE) of the chip configuration register
If a timeout error is detected while the TX49/H3 core, as the bus master, is gaining write access to the
If a timeout error is detected while another G-Bus master (the PCI controller or DMA controller) is
If the TRST* signal is deasserted, it is assumed that an EJTAG probe is connected, so the G-Bus
5-1
Chapter 5 Configuration Registers