TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 551

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

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20-7
21-5
21-5
22-2
22-4
22-7
Modified line 8 of Section 20.3, Initializing the Extended
EJTAG Interface
The above methods must be performed while the
MASTERCLK signal is being input. Also, externally fix
the TRST* signal to GND when not using an emulation
probe. The G-Bus Time Out Detection function is disabled
when the TRST* signal is deasserted. (Refer to Section
5.1.1.)
Figure 21.5.1 Timing Diagram: MASTERCLK
Figure 21.5.2 Timing Diagram: Power On Reset
Figure 22.1.1 Pinout Diagram (1/2)
Table 22.1.1 Pin Cross Reference by Pin Number (1/2)
Modified the pin name of the E6 pin.
SD[1]
Table 22.1.2 Pin Cross Reference by Pin Name (2/2)
Modified the pin name of the E6 pin.
SD[1]
VddIN, VddIO
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*
7
6
5
MASTERCL
DMAACK
[2]
CE[4]*
CE[5]*
DMAACK
[3]
CE[3]*
VddIO
0.8 V
0.2 V
Rev 1.1 Manual
CC
CC
CE[1]*
CE[2]*
ACE*
MASTERCLK Oscillation Stabilit
CE[0]*
VSS
BYPASSP
LL*
t
VddIO
SD[1]
VSS
MCP_PLL
t
MCP
7
VddIN
TOP
The above methods must be performed while the
MASTERCLK signal is being input.
The G-Bus Time Out Detection function is disabled when
the TRST* signal is deasserted. (Refer to Section 5.1.1.)
Changed a signal name in the figure and added a note.
* 1)
SDIN[1]
SDIN[1]
V
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*
7
6
5
CCInt
MASTERCLK
DMAACK
[2]
CE[4]*
CE[5]*
V
V
The difference of the stand up time of a power supply
within in 100 m seconds.
TMPR4937 Revision History
CCInt
CCInt
, V
Changes and Additions to Rev 1.1
CCIO
and V
must be first.
DMAACK
[3]
CE[3]*
VddIO
* 1)
0.8 V
0.2 V
CCIO
CE[1]*
CE[2]*
ACE*
CC
CC
MASTERCLK Oscillation Stabilit
must start up simultaneously, or
CE[0]*
VSS
BYPASSP
LL*
VddIO
SDIN[1]
VSS
t
MCP_PLL
t
MCP
VddIN
TOP