TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 330

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
10
9
8
7
6
5
Mnemonic
G2PM0EN
G2PM1EN
G2PM2EN
G2PIOEN
IRBER
SRST
Software Reset
Bus Error
Response Setting
During Initiator
Read
Initiator Memory
Space 0 Enable
Initiator Memory
Space 1 Enable
Initiator Memory
Space 2 Enable
Initiator I/O Space
Enable
Field Name
Figure 10.4.41 PCI Controller Configuration Register (2/3)
Soft Reset (Default: 0x0)
Performs PCI Controller software reset control. Data is also reloaded to the
Configuration Space Register from EEPROM or from the Configuration
Data Register. Please set this bit after the EEPROM Load End bit
(PCICSTATUS.E2PDONE) is set. Also, please use the software to clear
this bit at least four PCI Bus Clock cycles after Reset.
Other registers of the PCI Controller cannot be accessed while this bit is
set.
This bit differs from the Hardware Reset bit (HRST). The following register
values are not initialized.
• G2P Status Register (G2PSTATUS)
• PCI Bus Arbiter Status Register (PBASTATUS)
• PCI Controller Status Register (PCICSTATUS)
• Software Reset bit (PCICCFG.SRST)
• Load Configuration Register bit (PCICCFG.LCFG)
1: The PCI Controller is reset by the software.
0: The PCI Controller is not reset by the software.
Initiator Read Bus Error Response (Default: 0x1)
Bus error responses on the G-Bus are controlled when the following
phenomena indicated by the PCI Status, Command Register (PICSTATUS)
and the G2P Status Register (G2PSTATUS) occur during initiator Read
access.
Detected Parity Error (PCISTATUS.DPE)
Received Master Abort (PCISTATUS.RMA)
Received Target Abort (PCISTATUS.RTA)
Initiator Detected TRDY Time Out Error (G2PSTATUS.IDTTOE)
Initiator Detected Retry Time Out Error (G2PSTATUS.IDRTOE)
1: Responds with a Bus error on the G-Bus.
0: Does not respond with a Bus error on the G-Bus.
Initiator Memory Space 0 Enable (Default: 0x0)
Controls PCI initiator access to Memory Space 0.
1: Memory Space 0 is valid.
0: Memory Space 0 is invalid.
Initiator Memory Space 1 Enable (Default: 0x0)
Controls PCI initiator access to Memory Space 1.
1: Memory Space 1 is valid.
0: Memory Space 1 is invalid.
Initiator Memory Space 2 Enable (Default: Normal Mode: 0x0; PCI Boot
Mode: 0x1)
Controls PCI initiator access to Memory Space 2.
1: Memory Space 2 is valid.
0: Memory Space 2 is invalid.
Initiator I/O Space Enable (Default: 0x0)
Controls PCI initiator access to the I/O Space..
1: I/O Space is valid.
0: I/O Space is invalid.
(Normally terminates the Read transaction on the G-Bus. Read data is
invalid.)
10-72
Description
Chapter 10 PCI Controller
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W