TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 55

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Signal Name
3.
ADDR[19:0]
DATA[63:0]
BUSSPRT*
3.1
3.1.1
Signals
Pin Signal Description
that the pin is equipped with an internal pull-down resister. OD indicates an open-drain pin.
immediately after it is deasserted. Those signals which are selected by a configuration signal upon a reset
have the state selected by the configuration signal even when the reset signal is asserted.
In the following tables, asterisks at the end of signal names indicate active-low signals.
In the Type column, PU indicates that the pin is equipped with an internal pull-up resister and PD indicates
The Initial State column shows the state of the signal when the RESET* signal is asserted and
Input/output
Input/output
Signals Common to SDRAM and External Bus Interfaces
Output
Type
PU
PU
Table 3.1.1 Signals Common to SDRAM and External Bus Interfaces
Address
Address signals.
For SDRAM, ADDR[19:5] are used (refer to Sections “9.3.2.2” and “9.3.2.3 Address
Signal Mapping”).
When the external bus controller uses these pins, the meaning of each bit varies with the
data bus width (refer to Section “7.3.5 Data Bus Size”).
The ADDR signals are also used as boot configuration signals (input) during a reset. For
details of configuration signals, refer to Section “3.2 Boot Configuration”.
The ADDR signals are input signals only when the RESET* signal is asserted and
become output signals after the RESET* signal is deasserted.
Data
64-bit data bus.
The DATA[15:0] signals are also used as boot configuration signals (input) during a reset.
For details of configuration signals, refer to Section “3.2 Boot Configuration”.
Bus Separate
Controls the connection and separation of devices controlled by the external bus
controller to or from a high-speed device, such as SDRAM (refer to Section “7.6 Flash
ROM, SRAM Usage Example”).
H: Separate devices other than SDRAM from the data bus.
L: Connect devices other than SDRAM to the data bus.
Separation and connection are performed using external bidirectional bus buffers (such
as the 74xx245).
3-1
Description
Chapter 3 Signals
Initial State
Input
Input
High