TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 391

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

12.3.6
Watchdog Timer Mode
counter and judges an anomaly to exist if the counter is not cleared within a specified period of time.
Then, either the TX4937 is internally reset or an NMI is signaled to the TX49/H3 core. Set the Timer
mode field (TMTCR2.TMODE) of the Timer Control Register to “10” to set the timer to the Watchdog
Timer mode. This mode can only be used by Timer 2.
perform an internal reset or signal an NMI. Set this bit to “1” to select Watchdog Reset, or set it to “0”
to select NMI Signaling.
Watchdog Timer TMCPRA Match Status bit in the Timer Interrupt Status Register (TMTISR2.TWIS) is
set. Either the watchdog timer reset or NMI is issued if the Timer Watchdog Enable bit in the Watchdog
Timer Mode Register (TMWTMR2.TWIE) is set.
Register (CCFG.WDRST) is set. If the Watchdog Reset External Output bit in the Chip Configuration
Register (CCFG.WDREXEN) is cleared, the entire TX4937 is initialized but the configuration registers.
Setting the Watchdog Reset External Output bit (CCFG.WDREXEN) causes the WDRST* signal to be
asserted. This does not initialize the TX4937. The WDRST* signal remains asserted until the RESET*
signal is asserted. Assertion of the RESET* signal deasserts the WDRST* signal and initializes the
TX4937.
1.
2.
3.
Enable bit (TMTCR2.TCE) of the Timer Control Register while the Watchdog Timer Disable bit
(TMWTMR2.WDIS) of the Watchdog Timer Mode Register is set to “1”.
(TMTCR2.CCDE) of the Timer Control Register when the internal clock is being used as the counter
clock.
are two ways to clear this bit.
1.
2.
The Watchdog Timer mode is used to monitor system anomalies. The software periodically clears the
Use the Watchdog Reset bit (WR) of the Chip Configuration Register (CCFG) to select whether to
When the timer count reaches the value programmed in Compare Register A (TMCPRA2), the
When the watchdog timer reset is selected, the Watchdog Reset Status bit in the Chip Configuration
There are three ways of stopping NMI signaling from being performed.
It is possible to stop the counter when in the Watchdog Timer mode by clearing the Timer Counter
It is also possible to stop the counter by clearing the Counter Clock Divide Cycle Enable bit
It is not possible to directly write “0” to the Watchdog Timer Disable bit (TMWTMR2.WDIS). There
Clear the Watchdog Timer Interrupt Status bit (TMTISR2.TWIS) of the timer Interrupt Status
Register.
Clear the counter by writing “1” to the Watchdog Timer Clear bit (TMWTMR2.TWC) of the
Watchdog Timer Mode Register.
Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE) while the Watchdog Timer
Disable bit (TMWTMR2.WDIS) is still set.
Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.WDIS)
Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register
12-7
Chapter 12 Timer/Counter