TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 460

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TMPR4937XBG-300

Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPR4937XBG-300

Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
Quantity:
16 845
Part Number:
TMPR4937XBG-300
Manufacturer:
DSP
Quantity:
81
31:30
29:28
27:26
25:24
23:22
21:20
Bit
15.4.3
31
15
Mnemonic
IC31
IC15
R/W
R/W
0
0
IC31
IC30
IC29
IC28
IC27
IC26
30
14
Interrupt Detection Mode Register 1 (IRDM1)
29
13
Interrupt Source
Control 31
Interrupt Source
Control 30
Interrupt Source
Control 29
Interrupt Source
Control 28
Interrupt Source
Control 27
Interrupt Source
Control 26
IC30
IC14
R/W
R/W
Field Name
0
0
28
12
Figure 15.4.3 Interrupt Detection Mode Register 1 (1/3)
27
11
IC29
IC13
R/W
R/W
0
0
Interrupt Source Control 31 (Default: 00, R/W)
These bits specify the active state of SPI interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 30 (Default: 00, R/W)
These bits specify the active state of DMA1[3] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 29 (Default: 00, R/W)
These bits specify the active state of DMA1[2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 28 (Default: 00, R/W)
These bits specify the active state of DMA1[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 27 (Default: 00, R/W)
These bits specify the active state of DMA1[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 26 (Default: 00, R/W)
These bits specify the active state of PCIC1 interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
26
10
25
9
IC28
R/W
IC12
R/W
0
0
24
8
15-14
23
7
IC27
IC11
R/W
R/W
0
0
Explanation
22
Chapter 15 Interrupt Controller
6
0xF608
21
5
IC26
IC10
R/W
R/W
0
0
20
4
19
3
IC25
R/W
R/W
IC9
0
0
18
2
17
1
IC24
R/W
R/W
IC8
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
16
0
: Type
: Default
: Type
: Default

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