TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 54

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

(1) TX49/H3 Core: Consists of a CPU, System Control Coprocessor (CP0), Instruction cache, Data cache,
(2) EBUSC:
(3) DMAC0:
(4) DMAC1:
(5) SDRAMC: SDRAM Controller. Controls 4-channel SDRAM. Supports 64-bit data bus, 133 MHz
(6) PCIC:
(7) SIO:
(8) TMR:
(9) PIO:
(10) ACLC:
(11) IRC:
(12) EBIF:
(13) CG:
(14) G-Bus:
(15) IM-Bus:
(16) MB:
(17) TEST
The TX4937 has the following blocks.
Floating-point Unit (FPU), write buffer (WBU), Debugging Support Unit (DSU), and a G-Bus I/F.
•
•
•
•
FPU:
I-Cache: Instruction cache memory. 32 KB, 4-way set associative.
D-Cache: Data cache memory. 32 KB, 4-way set associative. You can select as a write policy
DSU:
External Bus Controller. Controls 8-channel ROM, SRAM, I/O.
Direct Memory Access Controller. Has 4 channels. Can transfer internal I/O device,
external I/O device, mutual memory data.
Direct Memory Access Controller. Has 4 channels. Can transfer internal I/O device, mutual
memory data.
operation, ECC/parity.
PCI Controller. Complies with PCI Local Bus Specification Revision 2.2. Supports 66 MHz
operation. Has an on-chip dedicated DMA Controller (PDMAC).
Serial I/O. This is a 2-channel asynchronous serial I/F.
Timer/counter. This is a 3-channel timer/counter.
Parallel I/O. Has an 8-bit dedicated port and an 8-bit shared port.
AC-link Controller. Is compliant to Audio CODEC '97 Revision 2.1 (AC'97).
Interrupt Controller.
External Bus Interface. Connects 20-bit External Address Bus or 64-bit External Data Bus
to SDRAMC or EBUSC.
Clock Generator. Has a built-in PLL and provides a clock to each TX4937 block.
TX4937 internal bus. This is a 64-bit, high-speed internal bus that is directly connected to
the TX49/H3 core.
TX4937 internal bus. This is a 32-bit, slow-speed internal bus that is connected to the G-
Bus via IMB.
G-Bus - IM-Bus Bridge
This is the internal diagnostic module.
An IEEE754-compliant single-precision or double-precision floating-point unit. Is
allocated as one coprocessor unit (CP1).
Write Back, Write Through No Write Allocate, or Write Through Write Allocate.
Debugging Support Unit. This is an on-chip debugging module.
2-2
Chapter 2 Configuration