TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 371

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

11.3.12 Multi-Controller System
shown below in Figure 11.3.4.
all Slave Controllers, then transmits and receives data with the selected Slave Controller. Slave
Controllers that were not selected will ignore this data.
frames whose Wake Up bit (WUB) is “0” are handled as data frames.
(1) The Master and Slave Controllers set the Mode field (UMODE) of the Line Control Register
(2) The Slave Controller sets the Reception Wake Up bit (RWUB) of the Line Control Register
(3) The Master Controller sets the Transmission Wake Up bit (TWUB) of the Line Control Register
(4) Since the Reception Wake Up bit (RWUB) is set, the Slave Controller generates an interrupt to the
(5) The Master Controller and the selected Slave Controller clear the Transmission Wake Up bit
(6) Transmit/Receive data between the Master Controller and the selected Slave Controller. Then,
The Multi-Controller System consists of one Master Controller, and multiple Slave Controllers as
In the case of the Multi-Controller System, the Master Controller transmits an address (ID) frame to
Data frames whose data frame Wake Up bits (WUB) are “1” are handled as address (ID) frames. Data
The data transfer procedure for the Multi-Controller System is as follows.
(SILCR) to “10” or “11” to set the Multi-Controller System mode. Also, the Slave Controller sets
the open drain enable bit (UODE) of the Line Control Register (SILCR), setting the TXD output
signal to open drain output.
(SILCR), making it possible to receive address (ID) frames from the Master Controller.
(SILCR), and transmits the address (ID) of the selected Slave Controller. This causes the address
(ID) frame to be transmitted. The Reception after Address Transmission Wake Up bit (RWUB) is
cleared, enabling reception of data frames.
CPU by receiving an address (ID) frame. The CPU compares its own address (ID) and the received
data together. If they do not match, the Reception Wake Up bit (RWUB) is cleared, making data
frame reception possible.
(TWUB) of the Line Control Register (SILCR), then set the mode that transmits data frames.
Slave Controllers that were not selected ignore data frames since the Reception Wake Up bit
(RWUB) is still set.
Figure 11.3.4 Example Configuration of Multi-Controller System
TXD
RXD
Slave #1
Master
RXD
TXD
RXD
Slave #2
11-11
TXD
Chapter 11 Serial I/O Port
RXD
Slave #3
TXD