TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 329

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TMPR4937XBG-300

Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPR4937XBG-300

Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant

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Quantity
Price
Part Number:
TMPR4937XBG-300
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TOSHIBA
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Manufacturer:
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31:28
27:16
15:12
Bit
11
31
15
10.4.43 PCI Controller Configuration Register (PCICCFG)
Mnemonic
Reserved
Reserved
GBWC
HRST
Reserved
G-Bus Wait
Counter Setting
Reserved
Hardware Reset
Field Name
28
12
Figure 10.4.41 PCI Controller Configuration Register (1/3)
HRST SRST IRBER
R/W
0x0
27
11
R/W
0x0
10
G Bus Wait Counter (Default: 0xFFF)
Sets the Retry response counter at the G-Bus during a PCI initiator Read
transaction.
When the initiator Read access cycle exceeds the setting of this counter, a
Retry response is sent to the G-Bus and the G-Bus is released. PCI Read
operation continues. This counter uses the G-Bus clock (GBUSCLK) when
operating.
When 0x000 is set, a Retry response is not sent to the G-Bus by a long
response cycle count.
When the G-Bus timeout count is used with the value other than the initial
value 4096 GBUSCLK, G-BUS timeout may occur before a Retry response
is sent.
When G-Bus timeout of the configuration register (CCFG.GTOT) is used
with the value other than the initial value (11), set the following maximum
values to the register.
GTOT value
Hard Reset (Default: 0x0)
Performs PCI Controller hardware reset control. EEPROM reloading is also
performed. This bit is automatically cleared when Reset ends. This is a
diagnostic function.
The PCI Controller cannot be accessed for 32 G-Bus clock cycles after this
bit is set.
1: Perform a hardware reset on the PCI Controller.
0: Do not perform a hardware reset on the PCI Controller.
10 (2048 GBUSCLK) : 0x7f0
01 (1024 GBUSCLK) : 0x3f0
00 ( 512 GBUSCLK) : 0x1f0
R/W
0x1
9
G2PM0EN G2PM1EN G2PM2EN
R/W
0x0
8
10-71
R/W
0x0
7
Maximum value of the register
R/W
0x0
6
Description
GBWC
R/W
0xfff
G2PIOEN
R/W
0x0
5
Chapter 10 PCI Controller
TCAR ICAEN LCFG
R/W
0x0
4
0xD170
R/W
0x0
3
R/W
0x0
2
Reserved
1
Read/Write
R/W
R/W
16
0
: Type
: Initial value
: Initial value
: Type

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