TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 419

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

14.3.6.5 Sample-data FIFO
14.3.6.6 Error Detection and Recovery
transmission and the FIFO has any room to fill data in, the FIFO issues a request via the REQ
latch. On the other side, when a transmission FIFO receives a data-request from the link-side, it
provides data with valid-flag set if it has any valid data. If it has no valid data, it responds with
valid-flag unset and an underrun error bit is set.
with valid-flag unset, in order to maximize the buffering effect. Therefore, the DMA size must be
the FIFO depth or more.
bits are driven to all ‘0’.
REQ latch. On the other side, when ACCTLEN allows that reception and the link-side issues a
data strobe, the FIFO stores the valid data. If the FIFO is full when it receives a data strobe, the
data is discarded and an overrun error bit is set.
reception, after DMA is finished, underrun and overrun will occur. The procedure described
below allows the software to determine whether an error has occurred during DMA operation.
(xxxxEHLT) bit before it starts a DMA channel. After it starts the DMA channel, it waits until
ACLC Interrupt Status Register (ACINTSTS)’s Underrun or Overrun Error (xxxxERR) bit is set.
When the event is detected, the software checks DMA Channel Control Register (DMCCRn)’s
Transfer Active (XFACT) bit and ACLC DMA Request Status Register (ACDMASTS)’s Request
(xxxxDMA) bit and determines the DMA completion status as follows.
DMCCRn.XFACT
For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that
At the transmit-data DMA start-up, until the FIFO becomes full, it responds to the link-side
The link-side drives the slot-valid bit and slot-data on AC-link. When underrun occurs, these
For a reception stream, as long as the FIFO has any valid data, the FIFO issues a request via the
In most usages, since the CODEC continuously requests sample-data transmission and
The software sets ACLC Control Enable Register (ACCTLEN)’s Error Halt Enable
To recover from error, disable and enable the stream via ACCTLEN, and restart the DMA.
Inactive
Inactive
Active
Table 14.3.9 DMA Completion Status Determination
Table 14.3.8 Transmission FIFO Depth
PCM L&R out
Surround L&R out
Center out
LFE out
Modem Line 1 out
Data-stream
ACDMASTS.xxxxDMA
Not Pending
14-13
Pending
FIFO Depth (Word)
*
Chapter 14 AC-link Controller
3
3
2
2
1
Completion Status
No Error during DMA
Underrun or Overrun
Underrun or Overrun