TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 109

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

7.3.6
Dynamic Mode
ACK*/Ready
ACK*/Ready
Static Mode
Access Mode
separately for each channel.
•
•
•
•
ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is
selected by the ACK*/Ready Mode bit (CCFG.ARMODE) of the Chip Configuration Register. The
mode selected is applied globally to all channels.
(1) ACK*/READY Dynamic mode (CCFG.ARMODE = 0)
(2) ACK*/Ready Static mode (CCFG.ARMODE = 0)
The following four modes are available as controller access modes. These modes can be set
Depending on the combination of modes in each channel, either of two modes in which the
Normal mode
Page mode
External ACK mode
Ready mode
This mode is selected in the initial state.
The ACK*/Ready signal automatically switches to either input or output according to the setting of
each channel. When in the Normal mode or the Page mode, the ACK*/Ready signal is an output
signal, and the internally generated ACK* signal is output. When in the External ACK* or Ready
mode, the ACK*/Ready signal becomes an input signal. The ACK*/Ready signal outputs High if
there is no access to the External Bus Controller. However, this signal may output Low during
access to SDRAM.
Please refer to the timing diagrams (Figure 7.5.23 and Figure 7.5.24) and be careful to avoid
conflicts when switching from output to input.
The internally generated ACK* signal is not output when in either the Normal mode or Page mode.
Therefore, the ACK*/Ready signal will not become an output in any channel.
Access using Burst transfer by the internal bus (G-Bus) is supported when in a mode other than the
Ready mode. However, the Ready mode is not supported.
PM
!0
!0
0
0
RDY
0
1
0
1
0
1
0
1
PWT:WT
Table 7.3.7 Operation Mode
!3f
!3f
⎯
⎯
⎯
⎯
⎯
⎯
3f
3f
External ACK*
External ACK*
Reserved
Reserved
READY
READY
Normal
Normal
7-9
Mode
Page
Page
Chapter 7 External Bus Controller
ACK*/READY
Pin State
Output
Output
Input
Input
Input
Input
Hi-Z
Hi-Z
⎯
⎯
Generated ACK*
Generated ACK*
Generated ACK*
Generated ACK*
Timing State
Access End
Ready Input
Ready Input
ACK* Input
ACK* Input
Internally
Internally
Internally
Internally
⎯
⎯
G-Bus Burst
Access
⎯
⎯
⎯
⎯
√
√
√
√
√
√