TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 229

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3.10
ECC Field
9.3.10.1 ECC/Parity Mode
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
ECC
separately for each channel using the ECC/Parity Mode field (SDCCRn.ECC) of the SDRAM
Channel Control Register. The ECC enable bit (ECCCR.ECCE) of the ECC Control Register must
be set in order to use the ECC function. No error detection, logging, or notification will be
performed if this bit is not set.
•
•
•
Table 9.3.5 shows the supported ECC/Parity functions. The ECC/Parity mode can be set
ECC + Scrub Mode
Even Parity Mode
Odd Parity Mode
Mode Name
The ECC/Parity Mode changes dynamically according to each channel setting.
Error checking is performed when writing data smaller than 64 bits when Memory Read
access is being performed while in the EC Mode, ECC Mode, or ECC + scrub mode.
Data correction is performed if the read data cause a single-bit error when in the ECC Mode
or the ECC + scrub mode. Data is read unchanged when in any other mode regardless of
whether or not an error occurs.
NOP Mode
ECC Mode
EC Mode
—
—
Table 9.3.5 ECC/Parity Mode
Disables the ECC/Parity function.
EC (Error Check) enable
Read: Performs only error checking. Correction is not performed.
Write: Generates check code.
ECC (Error Check and Correct) enable
Read: Performs error checking and correction.
Write: Generates check code.
ECC + scrub enable
Read: Performs error checking and correction. Corrected data is written back to
Write: Generates check code.
Even parity enable
Read: Performs error checking.
Write: Generates even parity.
Odd parity enable
Read: Performs error checking.
Write: Generates odd parity.
Reserved
Reserved
memory if an error occurs.
9-13
Chapter 9 SDRAM Controller
Description