TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 522

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C_BE[2]
IRDY*
VddIO
VSS
PCIAD
[15]
PCIAD
[11]
C_BE[0]
PCIAD[5]
PCIAD[2]
PCST[0]
PCST[3]
EEPROM_
CS
EEPROM_
SK
VSS
EEPROM_
DO
EEPROM_
DI
BWE[1]*
BWE[0]*
DMAACK
[1]
DMAACK
[2]
CE[4]*
CE[5]*
CE[7]*
SWE*
PIO[0]
PIO[1]
A
STOP*
VSS
FRAME*
PERR*
C_BE[1]
PCIAD
[12]
PCIAD[8]
PCIAD[6]
PCIAD[3]
PCIAD[0]
PCST[2]
PCST[5]
PCST[8]
TDO
DCLK
TCK
BWE[2]*
DMAREQ
[1]
DMAREQ
[2]
DMAACK
[3]
CE[3]*
VddIO
CE[6]*
BUSSPRT
*
PIO[2]
PIO[3]
B
PCIAD
[16]
PCIAD
[17]
DEVSEL*
LOCK*
PAR
PCIAD
[13]
PCIAD[9]
PCIAD[7]
VddIO
PCIAD[1]
PCST[1]
PCST[4]
PCST[7]
TPC[3]
TMS
TDI
BWE[3]*
VddIO
DMAREQ
[3]
CE[1]*
CE[2]*
ACE*
ACK*
VddIO
PIO[4]
PIO[5]
C
PCIAD
[18]
VddIO
TRDY*
VddIN
SERR*
VddIO
M66EN
VddIO
PCIAD[4]
VddIN
VddIO
VddIN
VddIO
TPC[2]
VddIO
DMAACK
[0]
VddIN
VSS
VddIN
CE[0]*
VSS
BYPASSP
LL*
VddIN
PIO[6]
VSS
PIO[7]
D
Figure 22.1.1 Pinout Diagram (1/2)
PCIAD
[19]
PCIAD
[20]
PCIAD
[21]
PCIAD
[22]
VSS
PCIAD
[14]
PCIAD
[10]
VSS
VSS
VSS
TRST*
VSS
PCST[6]
TPC[1]
VSS
DMAREQ
[0]
VSS
DMADON
E*
VSS
VddIO
SDIN[1]
VSS
VddIO
TIMER[1]
TIMER[0]
TCLK
E
PCIAD
[23]
VddIO
ID_SEL
C_BE[3]
VddIO
VddIN
NMI*
INT[0]
INT[1]
INT[2]
TOP View
Chapter 22 Pinout and Package Information
F
22-2
PCIAD
[24]
PCIAD
[25]
PCIAD
[26]
PCIAD
[27]
PCIAD
[28]
VddIN
RXD[0]
INT[3]
INT[4]
INT[5]
G
PCICLK
[0]
VddIO
PCIAD
[29]
VddIN
VSS
VSS
VddIO
CTS[0]*
RTS[0]*
TXD[0]
H
PCICLK
[1]
GNT[0]*
PCIAD
[30]
VSS
PCIAD
[31]
RXD[1]
CTS[1]*
RTS[1]*
TXD[1]
SCLK
J
HALTDOZE TEST[3]*
PCICLK
[2]
REQ[0]*
GNT[1]*
VddIN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VddIN
TEST[0]*
RESET*
K
PCICLK
[3]
GNT[2]*
REQ[2]*
VSS
REQ[1]*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TEST[1]*
TEST[2]*
TEST[4]*
SYSCLK
L
PCICLK
[4]
GNT[3]*
REQ[3]*
VddIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VddIN
VddIO
WDRST*
OE*
M
PCICLK
[5]
DATA[63]
VSS
VddIO
PME*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VddIO
VSS
DATA[0]
DATA[32]
DATA[1]
N