TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 175
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
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The sequence of Chain DMA transfer is as follows below.
Select DMA request signal
When performing external I/O or internal I/O DMA, set the DMA Request Select field
(PCFG.DMASEL) of the Pin Configuration Register.
Set the Master Enable bit
Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.
Structure of the DMA command Descriptor chain
Construct the DMA Command Descriptor Chain in memory.
Set the Count Register
Set “0” to the DMA Count Register (DMCNTRn) .
Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address
Increment Register (MMDAIRn).
Clear the DMA Channel Status Register (DMCSRn)
Clear the status of the previous DMA transfer.
Set the DMA Channel Control Register (DMCCRn).
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“A”
“B”
“C”
Figure 8.3.5 DMA Command Descriptor Chain
8-19
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“D”
“E”
Chapter 8 DMA Controller
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