TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 60

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Signal Name
Signal Name
Signal Name
CTS [1:0]*
RTS [1:0]*
RXD[1:0]
TXD[1:0]
SCLK
TIMER[1:0]
TCLK
WDRST*
PIO[15:8]
PIO[7:0]
3.1.6
3.1.7
3.1.8
Input/output
Input/output
Serial I/O Interface Signals
Timer Interface Signals
Parallel I/O Interface Signals
OD output
3-state
Output
Output
Output
Type
Type
Type
Input
Input
Input
Input
PU
PU
PU
PU
PU
PU
SIO Clear to Send
CTS* signals.
SIO Request to Send
RTS* signals.
SIO Receive Data
Serial data input signals.
SIO Transmit Data
Serial data output signals.
External Serial Clock
SIO clock input signal. SIO0 and SIO1 share this signal.
Timer Output
Timer output signals.
External Timer Clock
Timer input clock signal. TMR0, TMR1, and TMR2 share this signal.
Watchdog Reset
Watchdog reset output signal.
PIO Ports[15:8]
Parallel I/O signals.
PIO[15:8] share pins with the SDRAM ECC/parity signals (CB[7:0]). The boot
configuration signal on the ADDR[18] pin selects between PIO[5:8] and CB[7:0] (refer to
Section “3.3 Pin multiplex”).
PIO Ports[7:0]
Parallel I/O signals.
PIO[4:2] share pins with the AC-link interface signals (SDOUT, SDIN[0], and BITCLK).
The boot configuration signal on the ADDR[9] pin selects between PIO[4:2] and AC-link
interface signals (refer to Section “3.3 Pin multiplex”).
Table 3.1.8 Parallel I/O Interface Signals
Table 3.1.6 Serial I/O Interface Signals
Table 3.1.7 Timer Interface Signals
3-6
Description
Description
Description
Chapter 3 Signals
Initial State
Initial State
Initial State
Input
All Low
Input
All High
Input
All High
Input
Hi-Z
Input
Input
(other than
PIO[4])
Selected by
ADDR[9]
(PIO[4] only)
L: Input
H: All Low