TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 182

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
6:3
2
1
0
Mnemonic
FIFUM[3:0]
MSTEN
RRPT
FIFO Use Enable
[3:0]
Reserved
Round Robin
Priority
Master Enable
Field Name
Figure 8.4.1 DMA Master Control Register (2/2)
FIFO Use Enable [3:0] (Default: 0x0)
Each channel specifies whether to use 8-double word FIFO in Dual
Address transfer. FIFUM[n] corresponds to channel n.
Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more
information.
Round Robin Priority (Default: 0)
Specifies the method for determining priority among channels.
1: Round Robin method. Priority of the last channel used is the lowest,
0: Fixed Priority. Priority is fixed in the order Channel 0 > Channel 1 >
Master Enable (Default: 0)
This bit enables the DMA Controller.
1: Enable
0: Disable
Note: If the entire DMA Controller is disabled, then all internal logic
and the next previous channel has the next lowest priority. Round robin
is in the order Channel 0 > Channel 1 > Channel > Channel 3.
Channel 2 > Channel 3.
including the Bus Interface Logic and State Machine are reset.
8-26
Description
Chapter 8 DMA Controller
Read/Write
R/W
R/W
R/W
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