TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 334

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:11
Bit
2:0
10
31
15
9
8
7
6
5
4
3
10.4.45 PCI Controller Interrupt Mask Register (PCICMASK)
Mnemonic
PERRIE
SERRIE
PMEIE
GBEIE
TLBIE
NIBIE
ZIBIE
Reserved
Reserved
PME Detect
Interrupt Enable
Long Burst
Transfer Detect
Interrupt
Negative
Increment Burst
Transfer Detect
Interrupt Enable
Zero Increment
Burst Transfer
Detect Interrupt
Enable
Reserved
PERR* Detect
Interrupt Enable
SERR* Detect
Interrupt Enable
G-Bus Bus Error
Detect Interrupt
Enable
Reserved
Field Name
Figure 10.4.43 PCI Controller Interrupt Mask Register
11
PMEIE TLBIE NIBIE ZIBIE
R/W
0x0
10
PME* Signal Interrupt Enable (Default: 0x0)
When in the Host mode, this bit generates an interrupt when input of the
PME* signal is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Too Long Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Burst transfer by the on-chip DMA
Controller exceeding 8 DWORDs was detected.
1: Generates an interrupt.
0: Does not generate an interrupt
Negative Increment Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a negative direction Burst transfer by
the on-chip DMA Controller is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Zero Increment Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Burst transfer by the on-chip DMA
Controller without an address increment is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
PERR* Interrupt Enable (Default: 0x0)
This bit generates an interrupt when the Parity Error signal (PERR*) is
asserted.
1: Generates an interrupt.
0: Does not generate an interrupt.
SERR* Interrupt Enable (Default: 0x0)
This bit generates an interrupt when the System Error signal (SERR*) is
asserted.
1: Generates an interrupt.
0: Does not generate an interrupt.
G-Bus Bus Error Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Bus Error is asserted while the PCI
Controller is the G-Bus Master.
1: Generates an interrupt.
0: Does not generate an interrupt.
R/W
0x0
9
R/W
0x0
Reserved
8
10-76
R/W
0x0
7
Reserved
Description
6
PERRIE SERRIE
R/W
0x0
5
Chapter 10 PCI Controller
R/W
0x0
4
0xD178
GBEIE
R/W
0x0
3
2
Reserved
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
0
⎯
⎯
⎯
: Type
: Initial value
: Type
: Initial value