TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 230

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3.10.2 ECC Error Notification
fields, then error notification is performed as described below:
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generated if either an ECC multi-bit error or parity error is detected during any Read/Write access
while the Multi-bit Error Interrupt Enable bit (ECCCR.MEI) is set.
generated if an ECC single-bit error is detected during any Read/Write access while the Single-bit
Error Interrupt Enable bit (ECCCR.SEI) is set.
detected while the Single-bit Error bit (ECCSR.SBERR) is set, then the Single-bit Error bit
(ECCSR.SBERR) is cleared, error data is written for the multi-bit error, then error notification is
performed. If a single-bit error is detected while the Multi-bit Error bit (ECCSR.MBERR) is set,
the Single-bit Error bit (ECCSR.SBERR) is not set and not error data is written. However, the
single-bit error is corrected according to the usual procedure.
error is detected while the Multi-bit Error Bus Error Enable Bit (ECCCR.MEB) of the ECC
Control Register is set.
exception is generated. A nonmaskable interrupt is generated during Read-Modify-Write memory
Read access that is performed when writing from the TX49 core data that is smaller than 64 bits.
Bus error notification is sent to the appropriate bus master during Read/Write access from another
bus master.
When either an ECC error or a parity error occurs, error data is written into one of the following
The Multi-bit Error bit (ECCSR.MBERR) of the ECC Status Register is set and an interrupt is
The Single-bit Error bit (ECCSR.SBERR) of the ECC Status Register is set and an interrupt is
Multi-bit errors are assigned a higher priority than single-bit errors. If a multi-bit error is
The following error notification will also be performed if either an ECC multi-bit error or parity
During read access by the TX49 core, bus error notification is sent to the TX49 core and an
Error Address Field (ERRAD) in the ECC Status Register (ECCSR)
Error ECC/Parity Mode Field (ERRMODE)
Error Memory Width Field (ERRMW)
Error Syndrome Field (ERRS)
9-14
Chapter 9 SDRAM Controller