TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 85

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

12:10 PCIDIVMODE PCICLK
Bit
9:8
7:6
5:3
2
1
0
Mnemonic
ACEHOLD
ARMODE
ENDIAN
SYSSP
⎯
⎯
Frequency
Division Ratio
Reserved
SYSCLK
frequency
division ratio
Reserved
Endian
ACK*/READY
Mode
ACE Hold
Field Name
Figure 5.2.1 Chip Configuration Register (3/3)
Specifies the frequency division ratio of the PCI bus clock
output (PCICLK[5:0]) frequency to the clock frequency
(CPUCLK) of the TX49/H3 core.
001: PCICLK frequency = CPUCLK frequency ÷ 4
011: PCICLK frequency = CPUCLK frequency ÷ 4.5
101: PCICLK frequency = CPUCLK frequency ÷ 5
111: PCICLK frequency = CPUCLK frequency ÷ 5.5
000: PCICLK frequency = CPUCLK frequency ÷ 8
010: PCICLK frequency = CPUCLK frequency ÷ 9
100: PCICLK frequency = CPUCLK frequency ÷ 10
110: PCICLK frequency = CPUCLK frequency ÷ 11
Indicates the frequency division ratio of the SYSCLK
frequency to the G-Bus clock frequency (GBUSCLK).
LL: 00: SYSCLK frequency = GBUSCLK frequency ÷ 4
LH: 01: SYSCLK frequency = GBUSCLK frequency ÷ 3
HL: 10: SYSCLK frequency = GBUSCLK frequency ÷ 2
HH: 11: SYSCLK frequency = GBUSCLK frequency
Indicates the TX4937 endian mode setting.
L: 0 = Little endian mode
H: 1 = Big endian mode
Selects an ACK*/READY signal operation mode for the
external bus controller (refer to Section 7.3.6).
0 = ACK*/READY dynamic mode
1 = ACK*/READY static mode
Specifies the hold time of an address relative to the external
bus controller ACE* signal (refer to Section 7.3.4).
0 = Switch the address at the same time when the ACE*
signal is deasserted.
1 = Switch the address one clock cycle after the ACE* signal
is deasserted.
5-5
Description
⎯
⎯
Chapter 5 Configuration Registers
Initial Value Read/Write
ADDR[11:10]
,0
ADDR[14:13] R
ADDR[12]
0
1
⎯
⎯
R/W
R
R/W
R/W
⎯
⎯