TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 276

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.11 Error Detection, Interrupt Reporting
10.3.10.3 Dynamic Chain Operation
10.3.10.4 Data Transfer Size
10.3.11.1 Normal Operation Interrupt
M66EN Signal Assert Detect
corresponding Interrupt Enable Bit is set. The following tables list the name of each interrupt cause, the
Status bit, and the Interrupt Enable bit. Please refer to the explanation of each Status bit for more
information regarding each interrupt cause.
The PCI Controller reports the four following types of interrupts to the Interrupt Controller (IRC).
When each cause is detected, an interrupt is reported if the corresponding Status bit is set, and the
Descriptor Chain that is currently being processed when executing DMA data transfer. This is
done according to the following procedure.
1.
2.
3.
the transfer size of each G-Bus transaction in a DMA transfer. The transfer size can be selected
from one of the following: 1 DWORD, 1 QWORD, or 4 QWORD (Burst transfer).
PDMAC G-Bus Address Register (PDMGA) and the PDMAC PCI Bus Address Register
(PDMPA) is a 64-bit address boundary and the PDMAC Count Register (PDMCTR) setting is an
8-byte multiple. 1 DWORD must be selected as the transfer size in all other cases.
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•
•
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Name
It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command
The Transfer Size field (PDMCFG.XFERSIZE) of the PDMAC Configuration Register specifies
1 QWORD or 4 QWORD can only be selected as the transfer size when the setting of the
DMA Command Descriptor Chain Construction
Constructs a DMA Command Descriptor Chain in memory.
Addition of DMA Command Descriptor Chains
Substitutes the address of the command descriptor that is at the beginning of the descriptor
chain to be added into the Descriptor Chain Address field at the end of the DMA Command
Descriptor Chain that is currently performing DMA transfer.
Chain Enable bit checking
Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Configuration Register
(PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA
Command Descriptor indicated by the address stored in the PDMAC Chain Address Register
(PDMCA) is written to the PDMAC Chain Address Register (PDMCA)
Normal Operation Interrupt
PDMAC Interrupt
Power Management Interrupt
Error Detection Interrupt
P2GSTATUS
10-18
Status Bit
(Interrupt Number: 16, PCIC)
(Interrupt Number: 15, PDMAC)
(Interrupt Number: 23, PCIPME)
(Interrupt Number: 22, PCIERR)
M66EN
Chapter 10 PCI Controller
P2GMASK
Interrupt Enable Bit
M66ENIE