TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 49

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

(2) Direct Memory Access Controllers (DMAC)
(3) SDRAM Controller (SDRAMC)
(4) PCI Controller (PCIC)
devices. Each DMA Controller has 4 built-in DMA Channels.
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having 4 on-chip channels and supporting a variety of memory configurations, the SDRAM
Controller can support memory sizes of up to 4 GB (1 GB/channel).
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Revision 2.2.
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The TX4937 has two DMA Controllers for invoking DMA transfer with memory and I/O
The SDRAM Controller generates the control signals required for the SDRAM interface. By
The TX4937 has an on-chip PCI Controller that is compliant with PCI Local Bus Specification
Can set internal/external DMA requests
Supports as internal DMA requests DMA with the on-chip Serial I/O Controller or AC-link
Controller
Supports as external I/O DMA transfer modes using external DMA requests Single Address
transfer (Fly-by DMA) and Dual Address transfer
Supports transfer between external devices with a data bus width of 32 bits, 16 bits or 8 bits
and memory
Supports memory-memory copy mode that has no address boundary constraints
Can perform Burst transfer of up to 8 double words in a single read or write operation
Supports the Memory Fill mode that writes double-word data to the memory region
Supports Chain DMA transfer
Memory clock (SDCLK) frequencies from 50 MHz to 133 MHz (For relationship between
CPU clock and memory clock, see Section 6.1)
4 sets of independent memory channels
Supports 2-bank or 4-bank 16 MB, 64 MB, 128 MB, 256 MB, or 512 MB SDRAM
Can used Registered DIMM
Supports ECC or parity generation/check functions
Can select either 32-bit or 64-bit data bus width for each channel
Can set SDRAM timing for each channel
Supports TX49/H3 core critical word first access
Low power consumption mode: can select Self-refresh or Pre-charge power down
PCI Local Bus Specification Revision 2.2 compliant
32-bit PCI interface with maximum PCI Bus clock frequency of 66 MHz
Supports both the Target and Initiator functions
Can change the address mapping between the internal bus and PCI Bus
Has an on-chip PCI Bus arbiter and can connect up to 4 External Bus Masters
Has a function mounted for booting the TX4937 from memory on the PCI Bus
Has an on-chip 1-channel PCI Controller-dedicated DMA Controller (PDMAC)
1-3
Chapter 1 Overview and Features