TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 97

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

PCICLK[5:0]
PCICLKIN
PCICLKO
EEPROM_SK Output
SCLK
TCLK
BITCLK
TCK
DCLK
Clock
Input/Output
Output
Input
Internal signal Clock supplied to the PCI controller. PCICLKO is
Input
Input
Input
Input
Output
Clock supplied to devices on the PCI bus.
The PCICLKEN bit of the PCFG register can
disable the output of PCICLK.
The frequency depends on boot configuration
signals ADDR[11:10] or the PCIDIVMODE field of
the CCFG register.
Initial Value of PCIDIVMODE[0] is 0.
CCFG_PCIDIVMODE[2:0]
Note: PCICLK[5:0] can supply clock pulses at 66
PCI bus clock. The built-in PCI controller of the
TX4937 operates with this clock.
Note: To achieve an accurate phase match with
generated by PLL2 based on PCICLKIN.
PCICLKO has the same frequency and phase as
those of PCICLKIN (input pin).
Clock for serial EEPROM used to initially set the
PIC configuration.
Input clock for SIO. SCLK is shared by SIO0 and
SIO1.
Input clock for timers. TCLK is shared by TMR0,
TMR1, and TMR2.
Input clock for the AC-link controller.
The pin is shared with the PIO[2] signal.
Input clock for JTAG.
Clock output for the real-time debugging system.
=001: CPUCLK divided by 4
=011: CPUCLK divided by 4.5
=101: CPUCLK divided by 5
=111: CPUCLK divided by 5.5
=000: CPUCLK divided by 8
=010: CPUCLK divided by 9
=100: CPUCLK divided by 10
=110: CPUCLK divided by 11
or 33 MHz when the CPUCLK frequency is
set to 300.
The setting is: 011, 010
the external clock, PCICLK[5:0] or the PCI
clock output from another PCI device must
be supplied to PCICLKIN.
Table 6.1.1 TX4937 Clock Signals (2/2)
Description
6-3
Configuration Signals
ADDR[11:10]
ADDR[9]
(Refer to Section
Related
3.2.)
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Chapter 6 Clocks
(Refer to Chapters 5
CCFG.PCIDIVMODE
PCFG.PCICLKEN[5:0]
Related Registers
and 10.)
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