TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 7

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9. SDRAM Controller................................................................................................................................................. 9-1
10. PCI Controller....................................................................................................................................................... 10-1
8.5
9.1
9.2
9.3
9.4
9.5
9.6
10.1
8.4.8
8.4.9
8.4.10
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10
8.5.11
8.5.12
8.5.13
8.5.14
8.5.15
8.5.16
8.5.17
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
10.1.1
Timing Diagrams ......................................................................................................................................... 8-40
Characteristics................................................................................................................................................ 9-1
Block Diagram ............................................................................................................................................... 9-2
Detailed Explanation...................................................................................................................................... 9-3
Registers....................................................................................................................................................... 9-17
Timing Diagrams ......................................................................................................................................... 9-26
SDRAM Usage Example ............................................................................................................................. 9-42
Features ........................................................................................................................................................ 10-1
DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) .................................... 8-37
DMA Count Register (DM0CNTRn, DM1CNTRn).......................................................................... 8-38
DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ........................................................ 8-39
Single Address Single Transfer from Memory to I/O (32-bit ROM) ................................................. 8-40
Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-41
Single Address Single Transfer from I/O to Memory (32-bit SRAM)............................................... 8-42
Single Address Burst Transfer from Memory to I/O (32-bit ROM) .................................................. 8-43
Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ................................................ 8-44
Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-46
Single Address Single Transfer from I/O to Memory (16-bit SRAM)............................................... 8-47
Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) .............................. 8-48
Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) ............................ 8-49
Single Address Single Transfer from Memory to I/O (64-bit SRAM)............................................... 8-50
Single Address Single Transfer from I/O to Memory (64-bit SDRAM) ............................................ 8-51
Single Address Single Transfer from Memory to I/O of Last Cycle
when DMADONE* Signal is Set to Output ...................................................................................... 8-52
Single Address Single Transfer from Memory to I/O (32-bit SDRAM) ............................................ 8-53
Single Address Single Transfer from I/O to Memory (32-bit SDRAM) ............................................ 8-54
External I/O Device – SRAM Dual Address Transfer ....................................................................... 8-55
External I/O Device – SDRAM Dual Address Transfer .................................................................... 8-57
External I/O Device (Non-burst) – SDRAM Dual Address Transfer................................................. 8-59
Supported SDRAM configurations...................................................................................................... 9-3
Address Mapping................................................................................................................................. 9-4
Initialization of SDRAM ..................................................................................................................... 9-9
Initialization of Memory Data, ECC/Parity ....................................................................................... 9-10
Low Power Consumption Function ................................................................................................... 9-11
Bus Errors .......................................................................................................................................... 9-12
Memory Read and Memory Write ..................................................................................................... 9-12
Slow Write Burst................................................................................................................................ 9-12
Clock Feedback ................................................................................................................................. 9-12
ECC ................................................................................................................................................... 9-13
SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2)
0x8018 (ch. 3).................................................................................................................................... 9-18
SDRAM Timing Register (SDCTR) 0x8040 ..................................................................................... 9-20
SDRAM Command Register (SDCCMD) 0x8058 ............................................................................ 9-22
ECC Control Register (ECCCR) 0xA000.......................................................................................... 9-23
ECC Status Register (ECCSR) 0xA008............................................................................................. 9-25
Single Read (64-bit Bus).................................................................................................................... 9-26
Single Write (64-bit Bus) ................................................................................................................... 9-28
Burst Read (64-bit Bus) ..................................................................................................................... 9-30
Burst Write (64-bit Bus) .................................................................................................................... 9-31
Burst Write (64-bit Bus, Slow Write Burst) ....................................................................................... 9-32
Single Read (32-bit Bus).................................................................................................................... 9-33
Single Write (32-bit Bus) ................................................................................................................... 9-35
Low Power Consumption and Power Down Mode ........................................................................... 9-37
Overall ............................................................................................................................................... 10-1
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