TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 377

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

UBRK
31:16
Bit
31
15
14
13
12
11
10
15
9
8
R
0
11.4.3
UVALID
Mnemonic
14
R
1
UVALID
UBRK
UPER
UOER
UFER
TOUT
TDIS
ERI
These registers indicate the DMA or interrupt status information.
UFER UPER UOER
DMA/Interrupt Status Register 0 (SIDISR0)
DMA/Interrupt Status Register 1 (SIDISR1)
13
R
0
Reserved
Receive Break
Receive FIFO
Available Status
Frame Error
Parity Error
Overrun Error
Reception Error
Interrupt
Reception Time
Out
Transmission
Data Empty
Field Name
12
R
0
11
R
0
Figure 11.4.3 DMA/Interrupt Status Register (1/2)
R/W0C R/W0C R/W0C R/W0C R/W0C
ERI
10
0
UART Break (Default: 0)
This field indicates the break reception status of the next data in the
Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO)
updates the status.
0: No breaks
1: Detect breaks
UART Available Data (Default: 1)
This field indicates whether or not data exists in the Receive FIFO
(SIRFIFO).
0: Data exists in the Receive FIFO.
1: No data exists in the Receive FIFO.
UART Frame Error (Default: 0)
This field indicates the frame error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no frame errors.
1: There are frame errors.
UART Parity Error (Default: 0)
This field indicates the parity error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no parity errors.
1: There are parity errors.
UART Overrun Error (Default: 0)
This register indicates the overrun status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no overrun errors.
1: There are overrun errors.
Receive Data Error Interrupt (Default: 0)
This bit is immediately set to “1” when a reception error (Frame Error,
Parity Error, or Overrun Error) is detected.
Time Out (Default: 0)
This bit is set to “1” when a reception time out occurs.
Transmit DMA/Interrupt Status (Default: 1)
This bit is set when available space of the amount set by the Transmit FIFO
Request Trigger Level (TDIL) of the FIFO Control Register (SIFCR) exists
in the Transmit FIFO.
TOUT TDIS
9
0
Reserved
8
1
11-17
RDIS
7
0
STIS
6
0
Description
Reserved
5
0xF308 (Ch. 0)
0xF408 (Ch. 1)
Chapter 11 Serial I/O Port
4
RFDN
00000
R
Read/Write
16
R
R
R
R
R
R/W0C
R/W0C
R/W0C
0
⎯
: Type
: Initial value
: Type
: Initial value