TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 267

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
Figure 10.3.4 Address Conversion For Initiator (G-Bus → PCI Bus Address Conversion)
Address (PCIAddr[39:0]) is as follows below. GBASE[35:8], PBASE[39:8], and AM[35:8] each
represent the setting register of the corresponding access window indicated below in Table 10.3.2. The
“&” symbol indicates a logical AND for each bit, “||” indicates a logical OR for each bit, “!” indicates
logical NOT, and “|” indicates bit linking.
Switching Function). Table 10.3.3 shows the settings registers for these properties.
PCI Bus. 64-bit access to the I/O space is not supported.
accessed when the Critical Word First function of the TX49/H3 core was enabled.
When expressed as a formula, conversion of a G-Bus address (GBusAddr[35:0]) into a PCI Bus
Figure 10.3.4 illustrates this address conversion.
It is possible to set each space to valid/invalid or to perform Word Swap (see “10.3.7 Endian
When 64-bit access is made to the initiator memory space, two 32-bit Burst accesses are issued on the
Also, operation is not guaranteed if resources in the PCI space were made cacheable and were then
PCIAddr
PBASE
Table 10.3.2 Initiator Access Space Address Mapping Register
If (GBusAddr[35:8] & ! AM[35:8] == GBASE[35:8] & ! AM[35:8]) then
| ((PBASE[35:8] & ! AM[35:8]) || (GBusAddr[35:8] & AM[35:8]))
| GBusAddr[7:0];
G2PM0GBASE.BA[35:8]
G2PM1GBASE.BA[35:8]
G2PM2GBASE.BA[35:8]
G2PIOGBASE.BA[35:8]
GBusAddr
PCIAddr[39:0] = PBASE[39:36]
G-Bus Base Address
39
39
GBASE
AM
GBASE[35:8]
35
35
35
0 0 0 - - - - - - - - - - - 0 0 1 1 1 - - - - - - - - - - - - - - - - - - - -
Compare
G2PM0PBASE.BA[39:8]
G2PM1PBASE.BA[39:8]
G2PM2PBASE.BA[39:8]
G2PIOPBASE.BA[39:8]
PCI Bus Base Address
10-9
PBASE[39:8]
Chapter 10 PCI Controller
G2PM0MASK.AM[35:8]
G2PM1MASK.AM[35:8]
G2PM2MASK.AM[35:8]
G2PIOMASK.AM[35:8]
Address Mask
8
8
8
AM[35:8]
7
7
7
0x00
0x00
0x00
0
0
0
0
0