TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 425

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
7:6
5
4
3
2
1
0
Mnemonic
LOWPWR
WRESET
WAKEUP
RDYCLR
MICSEL
ENLINK
⎯
Reserved
Clear CODEC
Ready Bit
MIC Selection
Assert Warm
Reset
Enable Wake-up
Enable AC-link
low-power mode
Enable AC-link
Field Name
RDYCLR: Clear CODEC Ready Bit
MICSEL: MIC Selection.
WRESET: Assert Warm Reset.
WAKEUP: Enable Wake-up.
LOWPWR: Enable AC-link Low-power Mode.
ENLINK: Enable AC-link.
Figure 14.4.1 ACCTLEN Register (3/3)
W1C
W1S
W1S
W1S
W1S
W1S
R
R
R
R
R
0: No effect
1: Clear CODEC[1:0] ready bits
[Note: This bit should only be written to reevaluate the CODEC
0: Indicates that PCM L&R (Slot 3&4) is selected for audio reception.
1: Indicates that MIC (Slot 6) is selected for audio reception.
0: No effect
1: Selects MIC (Slot 6) for audio reception.
0: Indicates that warm reset is not asserted.
1: Indicates that warm reset is asserted.
0: No effect
1: Asserts warm reset.
[Note 1: Do not assert warm reset during normal operation.]
[Note 2: The software must guarantee the warm reset assertion
0: Indicates that wake-up from low-power mode is disabled.
1: Indicates that wake-up from low-power mode is enabled. While
0: No effect
1: Enables wake-up from low-power mode.
[Note: Do not enable wake-up during normal operation.]
0: SYNC and SDOUT signals are not forced to low.
1: SYNC and SDOUT signals are forced to low.
0: No effect
1: Forces SYNC and SDOUT signals low.
[Note: Do not enable AC-link low-power mode during normal
0: Indicates that the ACRESET* signal to AC-link is asserted.
1: Indicates that the ACRESET* signal to AC-link is not asserted.
0: No effect
1: Deasserts the ACRESET* signal to AC-link
[Note: The software must guarantee the ACRESET* signal
any SDIN signal is driven high, ACLC asserts ACLCPME interrupt
request to the interrupt controller.
ready status after power-down command is sent to CODEC.]
operation.]
assertion time meets the AC’97 specification (1.0 µs or
more).]
time meets the AC’97 specification (1.0 µs or more).]
14-19
Description
Chapter 14 AC-link Controller
Read/Write
W1S
R/W1S
R/W1S
R/W1S
R/W1S
R/W1S
⎯