TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 84
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TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
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20:17
Bit
23
22
21
16
15
14
13
Mnemonic Field Name
PCIMODE
DIVMODE
PCIARB
BEOW
PCI66
TOE
WR
⎯
PCI 66MHz
Mode
PCI
Operation
Mode
Reserved
CPUCLK
Frequency
Multiplication
Factor
Write-Access
Bus Error
Watchdog
Timer Mode
G-Bus
Timeout
Error
Detection
PCI Arbiter
Selection
Figure 5.2.1 Chip Configuration Register (2/3)
Used to inform the device connected to the PCI bus that a 66
MHz operation is to be performed. This bit is valid only when the
PCI controller of the TX4937 is in host mode. (Refer to Section
10.3.8.)
0 = Do not perform a 66 MHz operation.
1 = Perform a 66 MHz operation.
Indicates information about the operation mode of the TX4937
PCI controller. (Refer to Section 10.3.1.)
L: 0: Satellite mode
H: 1: Host mode
Indicates information about the frequency multiplication factor of
the TX49/H3 core clock (CPUCLK) to the MASTERCLK. This
field is set with a result of encoding an initial input value at
ADDR[3:0].
The PLL incorporated in the TX4937 multiplies the
MASTERCLK and supplies the resulting frequency to the
TX49/H3 core.
The value set in DIVMODE[3:0] is reflected in the EC field of the
TX49/H3 core Config register.
ADDR[3:0]:DIVMODE[3:0]
HHHH: 0100: CPUCLK freq. = 2 × MASTERCLK freq.
HHHL: 1111: CPUCLK freq. = 2.5 × MASTERCLK freq.
HHLH: 0101: CPUCLK freq. = 3 × MASTERCLK freq.
HHLL: 0110: CPUCLK freq. = 4 × MASTERCLK freq.
LHHH: 1101: CPUCLK freq. = 4.5 x MASTERCLK freq.
LHHL: ---- : Reserved
LHLH: ---- : Reserved
LHLL: ---- : Reserved
HLHH: 0000: CPUCLK freq. = 8 × MASTERCLK freq.
HLHL: 1011: CPUCLK freq. = 10 × MASTERCLK freq.
HLLH: 0001: CPUCLK freq. = 12 × MASTERCLK freq.
HLLL: 0010: CPUCLK freq. = 16 × MASTERCLK freq.
LLHH: 1001: CPUCLK freq. = 18 × MASTERCLK freq.
LLHL: ---- : Reserved
LLLH: ---- : Reserved
LLLL: ---- : Reserved
Indicates that a timeout error has occurred in the internal bus (G-
Bus) during a write bus transaction of the TX49/H3 core. This bit
corresponds to interrupt No. 1 in the interrupt controller.
0 = No error has occurred.
1 = An error has occurred.
Specifies how information will be reported in watchdog timer
mode (refer to Section 12.3.6).
0 = Generate an NMI exception.
1 = Generate a watchdog reset.
Specifies whether to detect and report a bus timeout error in the
internal bus (G-Bus) of the TX4937.
0 = Do not detect or report a bus timeout error.
1 = Detect and report a bus timeout error.
Indicates the PCI bus arbiter selection setting (refer to Section
10.3.12).
L: 0 = External PCI bus arbiter
H: 1 = Built-in PCI bus arbiter
5-4
Description
⎯
Chapter 5 Configuration Registers
Initial Value Read/Write
0
ADDR[19]
ADDR[3:0]
0
0
0
DATA[2]
⎯
R/W
R
R
R/W1C
R/W
R/W
R
⎯
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