TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 58

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Signal Name
Signal Name
DMAREQ[3:0]
DMAACK[3:0]
DMADONE*
PCICLK[5:0]
PCICLKIN
PCIAD[31:0]
C_BE[3:0]
PAR
FRAME*
IRDY*
TRDY*
STOP*
LOCK*
ID_SEL
3.1.4
3.1.5
Input/output
Input/output PCI Address and Data
Input/output Command and Byte Enable
Input/output Parity
Input/output Cycle Frame
Input/output Initiator Ready
Input/output Target Ready
Input/output Stop
DMA Interface Signals
PCI Interface Signals
Output
Type
Output
Type
Input
Input
Input
Input
PU
PU
DMA Request
DMA transfer request signals from an external I/O device.
The DMAREQ[2] signal shares the pin with the ACRESET* signal. The boot
configuration signal on the ADDR[9] pin selects between DMAREQ[2] and
ACRESET* (refer to Section “3.3 Pin multiplex”).
DMA Acknowledge
DMA transfer acknowledge signals to an external I/O device.
The DMAACK[2] signal shares the pin with the SYNC signal. The boot
configuration signal on the ADDR[9] pin selects between DMAACK[2] and
SYNC (refer to Section “3.3 Pin multiplex”).
DMA Done
DMADONE* is either used as an output signal that reports the termination of
DMA transfer or as an input signal that causes DMA transfer to terminate.
PCI Clock
PCI bus clock signals.
When these clock signals are not used, the pins can be set to H using the PCICLK
Enable field of the pin configuration register (PCFG.PCICLKEN[5:0]).
PCI Feedback Clock
PCI feedback clock input.
Multiplexed address and data bus.
Command and byte enable signals.
Even parity signal for PCIAD[31:0] and C_BE[3:0]*.
Indicates that bus operation is in progress.
Indicates that the initiator is ready to complete data transfer.
Indicates that the target is ready to complete data transfer.
The target sends this signal to the initiator to request termination of data transfer.
Lock
Indicates that the PCI bus master is locking (exclusively accessing) a specified memory
target on the PCI bus.
Initialization Device Select
Chip select signal used for configuration access.
This pin is not used in host mode. When the PCI Controller is configured in host mode,
this pin must be pulled down.
Table 3.1.5 PCI Interface Signals (1/2)
Table 3.1.4 DMA Interface Signals
Description
3-4
Description
Chapter 3 Signals
Input
(other than
DMAREQ[2])
Selected by ADDR[9]
(DMAREQ[2] only)
L: Input
H: Low
All High
(other than
DMAACK[2])
Selected by ADDR[9]
(DMAACK[2] only)
L: High
H: Low
Input
Initial State
Initial State
All High
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input