TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 234
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
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Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
Quantity:
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Part Number:
TMPR4937XBG-300
Manufacturer:
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R/W
RD
47
31
15
63:49
47:33
31:29
28:16
63
0
0
Bit
48
32
9.4.1
ECC
R/W
R/W
MT
14
0
Mnemonic
0
1)
AM[35:21]
BA[35:21]
ECC
Reserved
—
—
—
29
13
0
SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0)
the address mask in the high-order 32-bit portion of the register must be written first, followed by the
Channel Enable bit in the low-order 32-bit portion.
When the SDCCRn is programmed using a sequence of 32-bit store instructions, the base address and
R/W
ME
28
12
Base Address
Address Mask
ECC/Parity Mode
0
Field Name
R/W
SE
—
—
—
11
0
Figure 9.4.1 SDRAM Channel Control Register (1/2)
R/W
CE
10
0
1)
Base Address (Default: 0x01FC/0x0000)
Specifies the base address. The upper 15 bits [35:21] of the physical
address are compared to the value of this field.
(Note) Only the default for Channel 0 differs. Channel 0: 0x01FC, Others:
0x0000
Reserved
Address Mask (Default: 0x0000)
Sets the valid bits for address comparison according to the base address.
0: Bits of the corresponding BA field are compared.
1: Bits of the corresponding BA field are not compared.
Reserved
ECC/Parity mode (Default: 000)
Specifies the channel ECC/Parity type (refer to 9.3.10.1).
000: NOP Mode
001: EC Mode
010: ECC Mode
011: ECC + scrub Mode
100: Even Parity Mode
101: Odd Parity Mode
110: Reserved
110: Reserved
Reserved
Reserved
9
0x01FC/0x0000
0x0000
R/W
R/W
R/W
AM
BA
BS
8
0
Reserved
9-18
7
Reserved
6
Description
000
R/W
RS
1)
Chapter 9 SDRAM Controller
5
0x8008 (ch. 1)
0x8010 (ch. 2)
0x8018 (ch. 3)
4
000
R/W
CS
3
1)
2
Reserved
49
33
1
Reserved
Reserved
R/W
MW
48
32
16
0
1
Read/Write
R/W
R/W
R/W
:Type
:Initial value
:Type
:Initial value
:Type
:Initial value
:Type
:Initial value
⎯
⎯
⎯
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