TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 161

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.2
8.3.3
8.3.3.1
On-chip Registers
each register in detail.
•
•
External I/O DMA Transfer Mode
connected to the External Bus Controller.
The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains
The External I/O DMA Transfer Mode performs DMA transfer with external I/O devices that are
Shared Registers
DMMCR:
DMMFDR:
DMA Channel Register
DMCHARn:
DMSARn:
DMDARn:
DMCNTRn:
DMSAIRn:
DMDAIRn:
DMCCRn:
DMCSRn:
External Interface
Transfer Request Signal (DMAREQ[n]). On the other hand, the DMA Controller accesses external
I/O devices by asserting the DMA Transfer Acknowledge Signal (DMAACK[n]).
of the DMA Channel Control Register (DMCCRn) to select the signal polarity for each channel,
and can use the Edge Request bit (EGREQ) to select either edge detection or level detection for
each channel. The DMA Transfer Acknowledge signal (DMAACK[n]) can also use the
Acknowledge Polarity bit (ACKPOL) to select the polarity.
•
External I/O devices signal DMA requests to the DMA Controller by asserting the DMA
The DMA Transfer Request signal (DMAREQ[n]) can use the Request Polarity bit (REQPOL)
Please assert/deassert the DMAREQ[n] signal as follows below.
When level detection is set (DMCCRn.EGREQ = 0)
DMAACK[n] signal is asserted. Also, the DMAREQ[n] signal must be deasserted before the
CE*/CS* signal is deasserted. If this signal is asserted too soon, DMA transfer will not be
performed. If this signal is asserted or deasserted too late, unexpected DMA transfer may
result.
external I/O device that is currently asserting DMAACK[n], then deasserting DMAREQ[n].
The DMAREQ[n] signal must be continuously asserted until one SYSCLK cycle after the
During Dual Address transfer, we recommend detecting assertion of the CE* signal for the
DMA Master Control Register
DMA Memory Fill Data Register
DMA Chained Address Register
DMA Source Address Register
DMA Destination Address Register
DMA Count Register
DMA Source Address Increment Register
DMA Destination Address Increment Register
DMA Channel Control Register
DMA Channel Status Register
8-5
Chapter 8 DMA Controller