TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 83

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

R/W
WR
63:42
39:32
31:27
26:25
63
47
31
15
0
Bit
41
40
24
5.2.1
TOE
R/W
14
Mnemonic
0
WDREXEN
TINTDIS
WDRST
BCFG
GTOT
Reserved
PCIARB
DATA[2]
⎯
⎯
13
Reserved
R
Chip Configuration Register (CCFG)
input signal level and the corresponding register value are indicated.
For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial
ADDR[11:10]
12
Reserved
Watchdog
Reset Status
Watchdog
Reset External
Output
Boot
Configuration
Reserved
G-Bus Timeout
Time
Disable
TX49/H3 Core
Timer Interrupt
Field Name
PCIDIVMODE
R/W
27
Figure 5.2.1 Chip Configuration Register (1/3)
R/W
42
26
10
0
Watch Dog Reset Status (Initial Value 0, RW1C)
Indicates that a watchdog reset has occurred (refer to Section
12.3.6).
Initialized when CGRESET* is asserted.
0 = No watchdog reset has occurred.
1 = A watchdog reset has occurred
Watch Dog Reset External Enable (Initial Value 0, R/W)
Specifies whether to assert the WDRST* signal at a watchdog
reset (refer to Section 12.3.6).
Initialized when CGRESET* is asserted.
0 = Do not assert the WDRST* signal.
1 = Assert the WDRST* signal.
Set to 1 at a reset if the corresponding DATA[15:8] signal is
high.
Set to 0 at a reset if the corresponding DATA[15:8] signal is
low.
Specifies the number of G-Bus clock (GBUSCLK) cycles after
which a bus timeout error will occur on the internal bus (G-
Bus) of the TX4937.
11 = 4096 GBUSCLK
10 = 2048 GBUSCLK
01 = 1024 GBUSCLK
00 = 512 GBUSCLK
Indicates a value for indicating whether to enable the
TX49/H3 internal timer interrupt (refer to Section 15.3.5).
H: 0: The TX49/H3 internal timer interrupt is enabled.
L: 1: The TX49/H3 internal timer interrupt is disabled.
GTOT
R/W
11
WDRST
R/W1C R/W
41
25
Reserved
0
9
TINTDIS
~DATA[7]
WDREXEN
40
24
Reserved
R
0
8
PCI66
ADDR[14:13]
R/W
39
23
5-3
0
7
SYSSP
Description
R
ADDR[19]
PCIMODE
⎯
⎯
22
Chapter 5 Configuration Registers
R
6
PCI1-66
R/W
21
0
5
0xE000
Reserved
DATA[15:8]
20
BCFG
R
DIVMODE
3
ADDR[3:0]
ENDIAN
ADDR[12]
R
R
2
Initial Value Read/Write
0
0
DATA[15:8]
11
~DATA[7]
ARMODE
R/W
⎯
⎯
17
1
0
R/W1C : Type
BEOW
ACEHOLD
R/W : Type
48
32
16
0
0
1
R/W1C
R/W
R
R/W
R
: Type
: Initial value
: Type
: Initial value
: Initial value
: Initial value
⎯
⎯