TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 167

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.7.2
a0
a8
b0
b8
c0
c8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
40
48
50
58
60
f0
f8
(a) DMCCRn.USEXFSZ = “0”
63
Burst Transfer During Single Address Transfer
Controller cannot perform Burst transfer that spans across 32-double word boundaries.
Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size
(DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that
were specified by a Burst transfer. Therefore, the DMA Controller executes multiple Burst
transactions of a transfer size smaller than the specified transfer size. This division method
changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA
Channel Control Register.
Transfer Start address are 0xA8 and the transfer setting size (DMCCRn.XFSZ) is set to 4 double
words.
(DMCCRn.USEXFSZ) is “0”. In this case, first a three-double word transfer is performed up to
the address aligned to the transfer setting size. Then, four-double word transfer specified by the
transfer setting size is repeated. This setting is normally used.
is “1”. In this case, transfer is repeated according to the transfer setting size. Three-double word
transfer and one-double word transfer is only performed consecutively without releasing bus
ownership when transfer spans across a 32-double word boundary.
According to the SDRAM Controller and External Bus Controller specifications, the DMA
Figure 8.3.2 shows the Single Address Burst transfer status when the lower 8 bits of the
Panel (a) of this figure shows the situation when the Transfer Size Mode bit
On the other hand, panel (b) shows when the Transfer Size Mode bit (DMCCRn.USEXFSWZ)
Figure 8.3.2 Non-aligned Single Address Burst Transfer
0
3 Double Words
4 Double Words
4 Double Words
4 Double Words
4 Double Words
4 Double Words
DMCCRn.XFER = 4
32 Double Word Boundary
8-11
(b) DMCCRn.USEXFSZ = “1”
a0
a8
b0
b8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
40
48
50
58
60
Chapter 8 DMA Controller
c0
c8
f0
f8
63
0
4 Double Words
4 Double Words
(3 + 1) Double Words
4 Double Words
4 Double Words
4 Double Words
DMCCRn.XFER = 4