TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 228

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3.6
9.3.7
9.3.8
9.3.9
Bus Errors
•
•
current operation. Then, the current SDRAM cycle will end, remaining SDRAMC operations will be
aborted, a Pre-charge All command will be issued to SDRAM, then the SDRAMC will return to the Idle
state.
Memory Read and Memory Write
SDCS* signal is asserted in the case of the Read command, Write command, Pre-charge command, or
Mode Register Set command. The same set up time is observed even for active commands if the Active
Command Ready bit (SDCTR.DA) of the SDRAM Timing Register is set. Figure 9.5.1 is a timing
diagram of Single Read operation when the SDCTR.DA bit is cleared. Figure 9.5.2 is a timing diagram
of Single Read operation when the SDCTR.DA bit is set.
Single Write operation is terminated by the Auto Pre-charge Command.
Slow Write Burst
changes at each cycle during Burst Write operation (Figure 9.5.6). When the Slow Write Burst bit is set,
the data will change every other cycle (Figure 9.5.7).
setting of the RAS-CAS Delay bit (SDCTR.RCD) of the SDRAM Timing Register. The RAS-CAS
Delay bit setting becomes valid when Slow Write Burst access is invalid. The setting of the Slow Burst
bit does not have any effect on Read access.
Clock Feedback
attempt to directly latch Read data with the internal clock is made. With the TX4937, it is possible to
latch data using SDRAM clock SDCLKIN that is input from outside the chip. Please connect
SDCLKIN to one of the SDCLK[3:0] pins and the external source.
The SDRAMC detects bus errors in the following situations:
If a bus error occurs when accessing the SDRAMC, then the SDRAMC will immediately assert the
The RAS* signal, CAS* signal, WE*, signal, and ADDR[19:5] signal are set up 1 cycle before the
Burst or Single Read operation is terminated by the Pre-charge Active Bank command. Burst or
When the Slow Write Burst bit (SDCTR.SWB) of the SDRAM Timing Register is cleared, the data
When the Slow Write Burst bit is set, all Write accesses will operate as t
When performing Read access at fast rates like 100 MHz, there may be insufficient set up time if an
Bus time-out occurs during Read or Write operation to the SDRAMC
ECC 2-bit fault error or Parity error occurs during SDRAM Read operation
9-12
Chapter 9 SDRAM Controller
RCD
= 3t
CK
regardless of the