TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 302

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

FTRD
31:23
21:20
19:16
R/W
0x0
Bit
22
15
14
13
12
31
15
10.4.19 P2G Configuration Register (P2GCFG)
Mnemonic
R/W
FTA
0x0
14
MEM0PD
TPRBL
FTRD
PME
FTA
Reserved MEM0PD MEM1PD MEM2PD
13
Reserved
PME
Target Prefetch
Read Burst
Length
Reserved
Force Target
Retry/Disconnect
Force Target
Abort
Reserved
Memory 0
Window Prefetch
Disable
R/W
0x0
Field Name
12
Reserved
R/W
0x0
11
Figure 10.4.17 P2G Configuration Register (1/2)
R/W
0x1
10
PME (Default: 0x0)
When the PCI Controller is in the Satellite mode, writing “1” to this bit
signals a PME (Power Management Event) to the PCI Host device. The
PME* signal is asserted if the PME_Status bit of the PMCSR Register is
set and the PME_En bit of the PMCSR Register is set.
This bit is cleared when the PCI Host device writes a “1” to the PME_Status
bit of the PMCSR Register.
This bit is invalid when the PCI Contoller is in the Host mode since the
PME* signal is an input signal.
Target Prefetch Read Burst Length (Default: 0x3)
These bits set the number of DWORDS (32-bit words) to be read into the
data FIFO when prefetching is valid during a target memory Read
operation.
Extra data transferred to the data FIFO is deleted when performing a
memory Read operation of a PCI Bus transfer that is smaller than the set
size.
This setting is invalid when prefetching is disabled.
0x00: Access and transfer each 2 DWORDs of data to the target read FIFO.
0x01: Access and transfer each 4 DWORDs of data to the target read FIFO.
0x10: Access and transfer each 6 DWORDs of data to the target read FIFO.
0x11: Access and transfer each 8 DWORDs of data to the target read FIFO.
Force Target Retry/Disconnect (Default: 0x0)
The PCI Controller executes Retry Termination on a PCI Read access
transaction if this bit is set to “1”. This is a diagnostic function.
Force Target Abort (Default: 0x0)
The PCI Controller executes a Target Abort on a PCI Read access
transaction if this bit is set to “1”. This is a diagnostic function.
Memory 0 Window Prefetch Disable (Default: 0x0)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 0
Space is disabled when this bit is set to “1”. PCI Burst Read transactions
are not supported when prefetching is disabled.
Even if the setting of this bit is changed, prefetchable bits in the Base
Address Register of the PCI Configuration Space will not reflect this
change. We recommend using the default setting when the PCI Controller
is in the Satellite mode.
TOBFR TIBFR
R/W
0x0
9
R/W
0x0
8
10-44
23
7
R/W1S
PME
0x0
22
Description
0xD090
21
TPRBL
Chapter 10 PCI Controller
R/W
0x3
20
Reserved
19
Reserved
Read/Write
R/W1S
R/W
R/W
R/W
R/W
16
0
⎯
⎯
⎯
: Initial value
: Type
: Initial value
: Type