TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 96

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

MASTERCLK Input
CPUCLK
GBUSCLK
IMBUSCLK
SYSCLK
SDCLK[3:0]
SDCLKIN
Clock
Input/Output
Internal signal Clock supplied to the TX49/H3 core.
Internal signal Clock supplied to peripheral blocks on the G-Bus.
Internal signal Clock supplied to peripheral modules on the IM-
Output
Output
Input/output
Master input clock for the TX4937.
The TX4937 internal clock generator multiplies or
divides MASTERCLK to generate internal clock
pulses.
PLL1 in the TX4937 generates CPUCLK by
multiplying MASTERCLK. Boot configuration
signals ADDR[3:0] can set the frequency ratio of
CPUCLK to MASTERCLK.
ADDR[3:0]
HHHH = 2 times MASTERCLK
HHHL = 2.5 times MASTERCLK
HHLH = 3 times MASTERCLK
HHLL = 4 times MASTERCLK
LHHH = 4.5 times MASTERCLK
HLHH = 8 times MASTERCLK
HLHL = 10 times MASTERCLK
HLLH = 12 times MASTERCLK
HLLL = 16 times MASTERCLK
LLHH = 18 times MASTERCLK
PLL1 in the TX4937 generates GBUSCLK by
multiplying MASTERCLK. Boot configuration
signal ADDR[2] can set the multiplier value.
ADDR[2]
L = 4 times MASTERCLK
H = 1 times MASTERCLK
Bus.
The frequency of IMBUSCLK is half that of
GBUSCLK.
System clock output from the TX4937. Used by
the devices connected to the external bus
controller (EBUSC).
Boot configuration signals ADDR[14:13] can set
the frequency ratio of SYSCLK to GBUSCLK.
ADDR[14:13]
LL: GBUSCLK divided by 4
LH: GBUSCLK divided by 3
HL: GBUSCLK divided by 2
HH: GBUSCLK divided by 1
The SYSCLKEN bit of the PCFG register can
disable the output of SYSCLK.
Note: To use SYSCLK to access external
Clock supplied to SDRAM. The frequency of
SDCLK[3:0] is the same as that of GBUSCLK.
The SDCLKEN[3:0] field of the PCFG register can
disable the output of SDCLK[3:0] on a per bit
basis.
Reference clock used to latch input data signals
from SDRAM.
The clock output from SDCLK should be
connected to SDCLKIN via a feedback line
outside the TX4937.
devices, the SYSCLK rate must match the
EBUSC channel operating rate. For details,
refer to Section 7.3.8.
Table 6.1.1 TX4937 Clock Signals (1/2)
Description
6-2
Configuration Signals
ADDR[3:0]
ADDR[2]
ADDR[14:13]
(Refer to Section
Related
3.2.)
⎯
⎯
⎯
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Chapter 6 Clocks
(Refer to Chapters 5
CCFG.DIVMODE[3:0]
CCFG.DIVMODE[2]
CCFG.SYSSP
PCFG.SYSCLKEN
PCFG.DRVCK[3:0]
PCFG.SDCLKEN[3:0]
PCFG.DRVCKIN
(PCFG.SDCLKDLY)
(PCFG.SDCLKINEN)
Related Registers
and 10.)
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