TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 533

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

23.2 Notes on External Bus Controller
23.3 Notes on DMA Controller
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[Restriction]
[Violation]
<Conditions>
Output delay of DATA[63:0] depends on the external bus speed set with EBCCRn.SP. For details on it,
see 21.5.4 External Bus Interface AC Characteristics.
When burst transfer is performed during DMA transfer, the increment value setting for address is
restricted. For details, see 8.3.7 Single Address Transfer and 8.3.8 Dual Address Transfer.
Restrictions in dual address transfer by the DMA controller
address (DMSARn), that should be read, in all channels including it.
and write is continued to the same address until CPU terminates DMA transfer (0 is set to
DMCCRn.XFACT).
(1) FIFO is disabled. 0 is set to either one channel or more of FIFUM[n] (n=3 to 0) in DMMCR.
(2) The channel shown above (1) is set to dual address transfer. 0 is set to SNGAD in DMCCRn (n=3
(3) A bus error occurs during access to the destination address in the channel which satisfies both (1)
(4) When (3) is satisfied, single transfer (non-burst transfer) in dual address transfer mode (see
Setting the DMA master control register (DMMCRn) is restricted in the dual address transfer mode.
When a bus error occurs on a channel contained in DMAC, “all 0” may be written repeatedly to the
In this case, the address value (DMSARn) and count register value (DMCNTRn) are not changed,
This violation occurs in the following conditions.
to 0).
and (2). 1 is set to DESERR in DMCSRn (n=3 to 0).
Supplemental Remarks for details) performed in any channel causes the violation shown above.
When DMMCR.FIFUM[n]=0 is set in dual address transfer mode, single transfer (non-burst
transfer) is performed regardless of the value set to DMCCRn.XFSZ.
23-3
Chapter 23 Notes on Use of TMPR4937