TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 543

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Appendix A TX49/H3 Core Supplement
A.1
A.2
A.3
A.4
A.5
TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding the
TX49/H3 Core.
This section explains items that are unique to the TX4937 of the TX49/H3 Core. Please refer to the “64-bit
Processor ID
most recent information.
Interrupts
TX49/H3 Core. In addition, interrupt causes are reflected in other bits of the IP field. Please refer to Section
“15.3.5 Interrupt signalling” for more information.
Bus Snoop
Halt/Doze mode
which further reduces power consumption. Clearing the HALT bit of the Config Register makes it possible to
shift to the Halt mode by executing the WAIT instruction.
Memory access order
initiator access, and has a 2-stage Post Write buffer (Write buffer) for target access.
the address of that data after the Write is issued may be issued to the internal bus (G-Bus) before the Write.
Other accesses are issued in order.
executed will be complete on the internal bus.
issue source bus. Please refer to “10.3.6 Post Write Function” for more information regarding methods for
guaranteeing the completion of Write transactions of the Post Write Buffer.
PRId Register values of the TX4937 TX49/H3 Core are as follows.
These values may be changed at a later date. Please contact the Toshiba Engineering Department for the
Interrupt signalling of the on-chip interrupt controller is reflected in bit IP[2] of the Cause Register in the
The Bus Snoop function is not used with the TX4937 due to restrictions of the Bus Snoop specification.
The Doze mode is not necessary when the Bus Snoop function is not used. Please use the Halt mode,
The TX49/H3 Core has a 4-stage Write buffer, the PCI Bus Bridge (PCI Controller) has 4 stages for
When data enters the Write buffer of the TX49/H3 Core, Cache Refill Read operations that do not match
Executing the SYNC instruction guarantees that bus access invoked by a load/store instruction previously
The PCI Bus Bridge is issued by the issue destination bus in the order all bus accesses are issued on the
Processor Revision Identifier Register: 0x0000 2D30
FPU Implementation/Revision Register (FCR0): 0x0000 2D30
A-1
Appendix A TX49/H3 Core Supplement