TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 278

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.12 PCI Bus Arbiter
10.3.12.1 Request Signal, Grant Signal
10.3.12.2 Priority Control
arbiter (Internal PCI Bus Arbiter mode) or to use the External PCI Bus arbiter (External PCI Bus Arbiter
mode).
(PBACFG.PBAEN) of the PCI Bus Arbiter Configuration Register starts operation.
Five ports are used: one for the PCI Controller bus master and four for External Bus masters. The three
remaining ports are reserved for future expanded features.
Configuration settings (DATA[2] signal) during boot up select whether to use the on-chip PCI Bus
When in the Internal PCI Bus Abiter mode, setting the PCI Bus Arbiter Enable bit
The on-chip PCI Bus arbiter can arbitrate eight sets of PCI Bus usage requests from the Bus Master.
Request Output signal and the GNT[0]* signal becomes the Bus Usage Permission Input Signal.
Furthermore, the REQ[1]* signal can be used as an interrupt output signal to the external devices
(see 14.3.7 for more information).
the arbitration algorithm that determines the priority of Internal PCI Bus arbiter bus requests. The
round-robin with the lower priority (Level 2) consists of Masters W - Z, and the round-robin with
the high priority (Level 1), consists of Master A - D and Level 2 Masters. The PCI Bus Arbiter
Request Port Register (PBAREQPORT) specifies whether to allocate the PCI Controller and the
four External Bus Masters to Masters A-D or W - Z.
The four external Bus Masters are connected to the REQ[3:0] signal and the GNT[3:0]* signal.
Also, when in the External PCI Bus Master mode, the REQ[0]* signal becomes the PCI Bus
As illustrated below in Figure 10.3.8, a combination of two round-robin sequences is used as
(Prirority: High)
(Priority: Low)
Level 1
Level 2
Figure 10.3.8 PCI Bus Arbitration Priority
Master Z
Master A
10-20
Master B
Master W
Master Y
Chapter 10 PCI Controller
Level 2
Master C
Master D
Master X