TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 266

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.4
0xFF_FFFF_FFFF
0x00_0000_0000
•
•
Initiator Access (G-Bus → PCI Bus Address Conversion)
converted into the PCI Bus address is used to issue a Burst transaction on the PCI Bus. 36-bit physical
address (G-Bus addresses) are used on the G-Bus. Also, 40-bit PCI Bus addresses are used on the PCI
Bus.
10.3.3). The size of each window is variable. When Burst transactions are issued to these access
windows on the G-Bus, then that G-Bus address is converted into a PCI Bus address that is used to issue
a Burst transaction to the PCI Bus as the initiator. PCI memory access is issued when the access
window is the memory access window. PCI I/O access is issued when the access window is the I/O
access window. Dual access cycles are also issued to the PCI Bus when the PCI Bus address exceeds
0x00_FFFF_FFFF.
During PCI initiator access, the G-Bus address of the Burst transaction issued by the G-Bus that was
Three memory access windows and one I/O access window can be set in the G-Bus space (Figure
Retry response to PCI Configuration access will continue until the software sets the Target
Configuration Access Ready Bit (PCICFG.TCAR) of the PCI Controller Configuration Register.
Please use the software to set this bit after the software initialization process ends and the software
is ready to accept PCI configuration.
Interrupt Acknowledge
Interrupt acknowledge cycles are executed on the PCI Bus when the G2P Interrupt Acknowledge
Data Register (G2PINTACK) is read. The value returned by this Read becomes the interrupt
acknowledge cycle data.
Special Cycle
command issues special cycles on the PCI Bus when writing to the G2P Special Cycle Data
Register (G2PSPC). The written value is output as the special cycle data.
Configuration cycles will be accepted as the target only when in the Satellite mode. After reset,
This command issues interrupt acknowledge cycles as an initiator only when in the Host mode.
The TX4937 does not support interrupt acknowledge cycles as the target.
This command issues specialy cycles as the initiator only when in the Host mode. This
The TX4937 does not support special cycles as the target.
PCI I/O Space
Figure 10.3.3 Initiator Access Memory Window
Memory Access Window
I/O Access Window
0xF_FFFF_FFFF
0x0_0000_0000
10-8
G-Bus Space
Chapter 10 PCI Controller
0xFF_FFFF_FFFF
0x00_0000_0000
PCI Memory Space