TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 416

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

14.3.6.2 DMA Channel Mapping
14.3.6.3 Sample-data Format
PCM L&R out (3&4)
Surround L&R out (7&8)
Center out (6)
LFE out (9)
PCM L&R in (3&4) or Mic in (6)
Modem Line1 out (5)
Modem Line 1 in (5)
seven data-streams, or slots, on the AC-link frame, according to ACLC DMA Channel Selection
Register (ACDMASEL) setting as shown in Table 14.3.1. The pin configuration register allocates
these DMA channels of ACLC to the DMAC (DMA controller) channels according to Pin
Configuration Register (PCFG)’s DMA Request Selection (DMASEL[7:0]) bits as described in
section 8.3.1.
AC-link Slot Number
resides on the first 16 bits of the 20 bits assigned to each slot on AC-link. Each sample-data
register allows access by word (32-bit) unit only. Therefore the DMA count must be a multiple of
word. Note that the transmit-data DMA count also must be the FIFO depth (refer to Table 14.3.8)
or more for a reason described later.
right samples. For audio MIC stream, valid data is loaded in the same field as the left sample
while the other field is filled with ‘0’. For audio center, LFE, and modem line 1 streams, two
consecutive samples are packed into every word.
buffer follows the rules below.
•
•
•
ACLC uses four DMA request channels. These DMA channels are allocated to four out of
ACLC transmits/receives 16 bits per sample for each data slot shown in Table 14.3.1. The data
For audio PCM front and surround streams, every data-word is loaded with a couple of left and
The data format at the sample-data register is arranged so that the data format on the DMA
Refer to the sections 14.4.16 and later for the register format.
Each sample data is put in the byte order in which the CPU operates (big- or little-endian).
Samples are put in the time-sequential order at increasing addresses on memory.
For a DMA channel which couples left and right samples, each left sample precedes the
corresponding right sample.
Table 14.3.1 DMA Channel Mapping Modes
ACLC ch0
ACLC ch1
ACLC ch2
ACLC ch3
14-10
0
ACLC ch0
ACLC ch1
ACLC ch2
ACLC ch3
Chapter 14 AC-link Controller
1
ACDMASEL
ACLC ch0
ACLC ch1
ACLC ch2
ACLC ch3
2
ACLC ch0
ACLC ch1
ACLC ch3
ACLC ch2
3