TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 170
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
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a0
a8
b0
b8
c0
c8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
f0
f8
63
Source Address
(DMCCRn.USEXFSZ) is set to “0”, the lower 8 bits of the Transfer Start address for the transfer
source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are
set to (a) 0x28/(b) 0x30, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 double words.
three double words is performed up to the address that is aligned with the transfer setting size.
Then, transfer of eight double words that is specified by the transfer setting size is repeated.
only data up to the address that is aligned with the transfer setting size is read to the on-chip FIFO.
Then, data is written up to the address that is aligned with the transfer setting size as long as data
remains in the on-chip FIFO. Efficiency decreases since the transfer size is divided. Also, since
data may remain in the on-chip FIFO, Burst transfer of a Dual Address that uses the on-chip FIFO
simultaneously with another channel cannot be performed.
transfer. This in turn makes it possible to perform Burst access only for memory access during
DMA transfer with external I/O devices that cannot perform Burst transfer.
to the on-chip FIFO is divided into multiple 8-byte Single Read transfers, then transfer is
executed.
Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1)
Figure 8.3.4 shows Dual Address Burst transfer when the Transfer Size Mode bit
Panel (a) of this figure shows when the address offset is equivalent. In this case, first transfer of
On the other hand, panel (b) show when the address offset is not equivalent. In this case, first
Using the Burst Inhibit bit makes it possible to mix Burst transfer with 8-Double-Word Single
When the Source Burst Inhibit bit (DMCCRn.SBINH) is set, data read from the Source Address
0
FIFO (8 Double Words)
8-14
Chapter 8 DMA Controller
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
a0
a8
b0
b8
Destination Address
63
0
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