TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 549
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
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Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
Quantity:
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Part Number:
TMPR4937XBG-300
Manufacturer:
DSP
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Table 8.3.3 Channel Register Setting Restrictions During
Dual Address Transfer
<DMSAIRn>
8/0/-8
Figure 9.4.4 ECC Control Register (1/2)
Figure 9.4.4 ECC Control Register (1/2)
Figure 9.4.4 ECC Control Register (1/2)
Modified the description of the DEEC (Diagnostic ECC)
field.
The value set by this field is output from CB[7:0] as the
check code when the ECCDM bit is set to “Enable.”
Figure 9.4.5 ECC Status Register
Figure 9.6.2 168-pin DIMM Connection Example
55
63
15
—
ADDR[16:5]
ADDR[18]
ADDR[17]
—
Rev 1.1 Manual
—
0x10
FRRS
0x10
R
R
R
A[11:0]
BA0
BA1
DQMB[7:0]
—
128MB un
—
48
56
—
8
5
8/0/-8
Table 8.3.3 Channel Register Setting Restrictions During
Dual Address Transfer
Added the following note.
The value set by this field is output from CB[7:0] as the
check code when the
: When DMSAIRn is set to 0, read access from source
device is performed only one time per transmission
specified by DMCCRn.XFSZ. For this reason, transfer
can not be performed burst transfer to the I/O device
which performs FIFO operation.
TMPR4937 Revision History
55
Changes and Additions to Rev 1.1
63
15
—
ADDR[16:5]
ADDR[19]
ADDR[18]
—
DM
VERNO
—
bit is set to “Enable.”
MDLNO
0x10
ERRS
0x10
R
A[11:0]
BA0
BA1
DQMB[7:0]
—
128MB un
—
48
56
—
8
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