TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 539

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TMPR4937XBG-300

Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPR4937XBG-300

Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant

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Part Number:
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TOSHIBA
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Module
G-Bus
[Restriction]
[Violation]
<Conditions>
(CP0)
[Workarounds]
TX49
Reg.
Restriction when Initiator Write by PDMAC and Target Read conflict.
<Conditions>.
PCI Controller of the target product and a Target Read transaction to the target product by the a device
on the PCI Bus conflict, there are cases when the Target Read data is corrupted.
(1) In the PCI Controller of the above target product:
(2) The internal bus (G-Bus) of the target product is accessed continuously in the following order.
(3) The target of the Target Read in (2) is a register on the G-Bus
register on the G-Bus is a register with the 0x8000 to 0xEFFF offset address.
Don’t perform Target Read from a register on the G-Bus when the condition is the following
When an Initiator Write transaction using PDMAC (PCI Dedicated DMA Controller) mounted in the
Do not perform Target Read access from a register on the G-Bus under the above conditions. The
A. PDMAC performs an Initiator Write transaction to a device on the PCI Bus.
B. Device on the PCI Bus becomes the Bus Master and performs a Target Read on the target
When the two above accesses conflict,
(a) PDMAC reads the Initiator Write data on the G-Bus.
(b) TC (Target Controller) reads data from the G-Bus because of a Target Read request.
However, there is no corresponding register on the Internal Bus (IM-Bus).
G-Bus
product.
TX4937
(b)
(a)
SDRAMC
PDMAC
EBIF
TC
B. Target Read
23-9
Chapter 23 Notes on Use of TMPR4937
SDRAM
A. PDMAC Initiator Write
Device 1 on
etc
PCI Bus
Data
Device 2 on
PCI Bus
Memory Bus
PCI Bus

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