TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 190

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:36
35:0
Bit
8.4.5
63
47
31
15
Mnemonic
DADDR
DMA Destination Address Register (DM0DARn, DM1DARn)
Offset Address: DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3)
Reserved
Destination
Address
Field Name
Figure 8.4.5 DMA Destination Address Register
DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3)
Destination Address (Default: undefined)
This register sets the physical address of the transfer destination during
Dual Address transfer. This register is ignored during Single Address
transfer.
Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer”
for more information.
During Burst transfer, the value changes only by the size of data
transferred during each single bus operation. During Single transfer, the
value only changes by the value specified by the DMA Destination Address
Increment Register (DMDAIRn).
Reserved
DADDR[31:16]
DADDR[15:0]
Reserved
8-34
R/W
R/W
⎯
⎯
Description
Chapter 8 DMA Controller
36
35
DADDR[35:32]
R/W
⎯
Read/Write
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value