TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 286

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

19:10
Bit
24
23
22
21
20
9
8
7
6
5
4
3
2
Mnemonic
SEREN
PEREN
MWIEN
FBBCP
66MCP
FBBEN
MDPE
STPC
VPS
BM
SC
CL
Master Data
Parity Error
Fast Back-to-
Back Capable
Reserved
66 MHz Capable
Capabilities List
Reserved
Fast Back-to-
Back Enable
SERR* Enable
Stepping Control
Parity Error
Response
VGA Palette
Snoop
Memory Write
and Invalidate
Enable
Special Cycles
Bus Master
Field Name
Figure 10.4.2 PCI Status, Command Register (2/3)
Master Data Parity Error (Default: 0)
Indicates the a parity error occurred when the PCI Controller is the PCI
initiator. This bit is not set when the PCI Controller is the target.
This bit is set when all of the three following conditions are met.
• It has been detected that the PERR* signal was set either directly or
• The PCI Controller is the Bus Master for a PCI Bus transaction during
• The Parity Error Response bit of the PCI Status Command Register
Fast Back-to-Back Capable (Fixed Value: 1)
Indicates whether target access of a fast back-to-back transaction can be
accepted. Is fixed to “1”.
66 MHz Capable (Fixed Value: 1)
Indicates the 66 MHz operation is possible. Is fixed to “1”.
Capabilities List (Fixed Value: 1)
Indicates that the capabilities list is being implemented. Is fixed to “1”.
Fast Back-to-Back Enable (Default: 0)
Indicates that issuing of fast back-to-back transactions has been enabled.
1: Enable
0: Disable
SERR* Enable (Default: 0)
Enables/Disables the SERR* signal.
The SERR* signal reports that either a PCI Bus address parity error or a
special cycle data parity error was detected. The SERR* signal is only
asserted when the Parity Error Response bit is set and this bit is set.
1: Enable
0: Disable
Stepping Control (Fixed Value: 0)
Indicates that stepping control is not being supported.
Parity Error Response (Default 0)
Sets operation when a PCI address/data parity error is detected.
A parity error response (either when the Parity Error Response bit
(PCISTATUS.PEREN) of the PERR* Signal Assert or PCI Status,
Command Register is set, or the SERR* signal is asserted) is performed
only when this bit is set.
When this bit is cleared, the PCI Controller ignores all parity errors and
continues the transaction process as if the parity of that transaction was
correct.
1: Parity error response is performed.
0: Parity error response is not performed.
VGA Palette Snoop (Fixed Value: 0)
Indicates that the VGA palette snoop function is not supported.
Memory Write and Invalidate Enable (Default: 0)
Controls whether to use the Memory Write and Invalidate command instead
of the Memory Write command when the PCI Controller is the initiator.
Special Cycles (Fixed Value: 0)
Indicates that special cycles will not be accepted as PCI targets.
Bus Master (Default: 0/1)
The default is only “1” when in the PCI Boot mode and in the Host mode.
1: Operates as the Bus Master.
0: Does not operate as the Bus Master.
indirectly.
which an error occurred.
(PCISTATUS.PEREN) has been set.
10-28
Description
Chapter 10 PCI Controller
Read/Write
R/W1C
R
R
R
R/W
R/W
R
R/W
R
R/W
R
R/W
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