TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 104

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

7.3.2
ADDR[14:13]
ADDR[8]
ADDR[7:6]
DATA[5]
DATA[4]
DATA[1:0]
Pin Name
⎯
⎯
Global/Boot-up Options
use global options that make settings common to all channels.
external pins (Boot pins) during reset.
“5.2.1 Chip Configuration Register” for more information.)
In addition to the settings made separately for each channel, the Channel Control Registers can also
External Bus Controller Channel 0 can be used as a Boot memory channel. Channel 0 is set by the
These settings are summarized below in Table 7.3.1. (Please refer to “3.3 Configuration signals” and
CCFG.ARMODE
CCFG.ACEHOLD
CCFG.SYSSP
EBCCR0.ME
EBCCR0.SP
EBCCR0.BC
EBCCR0.WT[0]
EBCCR0.BSZ
Set Register
Table 7.3.1 Global/Boot-up Options
Selects the operation mode of the ACK*/READY signal.
0 = ACK*/READY Dynamic mode (Default)
1 = ACK*/READY Static mode
Sets the address hold time relative to the ACE* signal.
0: Address changes simultaneous to deassertion of the ACE* signal.
1: Address changes 1 clock cycle after deassertion of the ACE* signal.
Specifies the division ratio of the SYSCLK output relative to the internal
bus clock (GBUSCLK).
00: 1/4 speed (1/4 the GBUSCLK frequency)
01: 1/3 speed (1/3 the GBUSCLK frequency)
10: 1/2 speed (1/2 the GBUSCLK frequency)
11: Full speed (same frequency as the GBUSCLK frequency)
Specifies whether to enable or disable Channel 0.
0: Disable this channel as a Boot channel.
1: Enable this channel as a Boot channel.
Specifies the operation speed of Channel 0.
00: 1/4 Speed mode
01: 1/3 Speed mode
10: 1/2 Speed mode
11: Full Speed mode
When accessing Channel 0, specifies whether to use the BWE[3:0] signal
as a Byte Enable signal (BE[3:0]) or to use it as a Byte Write Enable
signal (BWE[3:0]).
0: Byte Enable mode
1: Byte Write Enable mode
Specifies the Channel 0 access mode.
0: Normal mode (DATA[4] = H)
1: External ACK mode (DATA[4] = L)
Specifies the memory bus width of Channel 0.
00: Reserved
01: 32-bit width
10: 16-bit width
11: 8-bit width
(Default)
7-4
Chapter 7 External Bus Controller
Explanation